1 A New Enhanced Approach to Technology Mapping Alan Mishchenko Presented by: Sheng Xu May 2 nd 2006

2 Outline Background and Motivation New Mapping Flow –Creating the starting AIG –Computing k-feasible cuts –Boolean matching –Mapping internal nodes –Selecting delay-optimal mapping –Area recovery Supergates Summary

3 Background and Motivation Existing Problems: –Quality of Technology Mapping –Long Run time Proposed Mapping Method Based On FRAIG –Graph covering Vs. constructive decomposition –DAG-based Vs. tree-based –Boolean matching Vs. structural matching –Combination of algebraic and Boolean methods –New algorithm to enumerate subgraphs to be matched –Delay-optimal mapping, followed by area recovery

4 Background and Motivation (Continued) Basic Concepts –Subject Graph, Object Graph –AIG, FRAIG –Algebraic Approach, Boolean Approach –Netlist –Internal Nodes, Cuts, function of a cut –… More explanation later

5 Outline Background and Motivation New Mapping Flow –Creating the starting AIG –Computing k-feasible cuts –Boolean matching –Mapping internal nodes –Selecting delay-optimal mapping –Area recovery Supergates Summary

6 Creating the starting AIG Two methods –One Netlist Example: Convert p = abcd into AIG signal delays: D(a) = 4, D(b) = 3, D(c) = 3, D(d) = 5. Solution: p = ((a(bc))d), and D(p) = 6 –Multiple Netlists Contain choice node(s)

7 Computing k-feasible cuts Cuts (of node n1): –{n2, n3}, {n2, n5, n6} –Is {n4, n5} a Cut? Redundant/Irredundant –Is there any redundant cut of n1? Cut Set –What’s the n2 cut set? K-feasible Cuts –What’s the two-feasible cuts of node n2?

8 Boolean Matching comparing the Boolean function of the cut with those of the library gates –* assignment as a by product of matching

9 Boolean Matching (Continued) NPN-equivalent/N-equivalence The truth table and Canonical form –Example: phase how phase transform the bit string? How is Boolean Matching performed? –Pre-compute –Matching

10 Mapping internal nodes Compute all nodes arrival times Compute all cuts arrival times Compute all gate arrival times Dual-rail Matching of each node

11 Select Delay-Optimal Mapping and Area Recovery Delay-Optimal –After all AIG nodes are mapped –Decide positive or negative polarity Area Recovery is required to achieve area improvement after delay optimal

12 Outline Background and Motivation New Mapping Flow –Creating the starting AIG –Computing k-feasible cuts –Boolean matching –Mapping internal nodes –Selecting delay-optimal mapping –Area recovery Supergates Summary

13 Supergate What is supergate? To increase the diversity of Boolean functions Generate before mapping and add into library Compact save format reduce run time Generate Supergates recursively with constraints

14 Summary Combination of Boolean and algebraic methods. Boolean Matching Improve Mapping Quality Shorter Run-Time Future work: –Multiple Netlist –Exploring the role of don’t-cares in Boolean matching