© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 4 Data Movement Instructions by Barry B. Brey

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e MOV et.al. MOV is still the main data transfer instruction, but there are many variations that perform special tasks such as PUSH and POP. MOV is still the main data transfer instruction, but there are many variations that perform special tasks such as PUSH and POP. We do not often code in hexadecimal machine language, but an understanding tends to help with learning the instruction set and the form of instructions in the memory. We do not often code in hexadecimal machine language, but an understanding tends to help with learning the instruction set and the form of instructions in the memory.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Instruction Modes Instructions operate in the 16- or 32-bit mode. 16-bit mode instructions are used in DOS and 32-bit mode instructions are used in Windows. Instructions operate in the 16- or 32-bit mode. 16-bit mode instructions are used in DOS and 32-bit mode instructions are used in Windows. A prefix is used to switch between modes for one instruction at a time. A prefix is used to switch between modes for one instruction at a time. The register override prefix is 66H and is a byte that precedes the opcode in the memory, The register override prefix is 66H and is a byte that precedes the opcode in the memory, The address override prefix is a 67H and like 66H precedes the opcode in the memory. The address override prefix is a 67H and like 66H precedes the opcode in the memory.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The register size prefix switches from 8- and 16-bit registers in the 16-bit mode to 8- and 32-bit registers. The register size prefix switches from 8- and 16-bit registers in the 16-bit mode to 8- and 32-bit registers. The register size prefix switches from 8- and 32-bit registers to 8- and 16-bit registers in the 32-bit mode. The register size prefix switches from 8- and 32-bit registers to 8- and 16-bit registers in the 32-bit mode. (DOS)MOV EAX,EBX ;reg prefix used (Windows) MOV AX,BX ;reg prefix used

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The Opcode

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Fields of an Instruction The D bit in the first byte of an instruction is the direction of data flow either from or to R/M from REG. If D = 0 REG  R/M and if D = 1 R/M  REG The D bit in the first byte of an instruction is the direction of data flow either from or to R/M from REG. If D = 0 REG  R/M and if D = 1 R/M  REG The W bit in the first byte of the opcode either specifies a word (16-bit mode) or a doubleword (32-bit mode). W = 0 byte and W = 1 word/doubleword The W bit in the first byte of the opcode either specifies a word (16-bit mode) or a doubleword (32-bit mode). W = 0 byte and W = 1 word/doubleword

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The MOD field in the second byte specifies how R/M is used and wether a displacement exists. The MOD field in the second byte specifies how R/M is used and wether a displacement exists. R/M R/M MOD = 00 memory no displacement MOD = 00 memory no displacement MOD = 01 memory 8-bit displacement MOD = 01 memory 8-bit displacement MOD = 10 memory 16/32-bit displacement MOD = 10 memory 16/32-bit displacement MOD = 11 register MOD = 11 register

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The REG contains the register The REG contains the register The R/M field contains a register or a memory addressing mode as in [BX], etc. The R/M field contains a register or a memory addressing mode as in [BX], etc. Luckily we do not often need to code into hexadecimal form, that is why we have an assembler. The reason this is explained in the text is so that a feeling for the way instructions are coded is understood and why different instruction contain different numbers of bytes. This knowledge may help when generating efficient code. Luckily we do not often need to code into hexadecimal form, that is why we have an assembler. The reason this is explained in the text is so that a feeling for the way instructions are coded is understood and why different instruction contain different numbers of bytes. This knowledge may help when generating efficient code.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Segment Register Moves Although we do not often directly address segment registers it is important to understand the limitations of the segment register MOV instruction. Although we do not often directly address segment registers it is important to understand the limitations of the segment register MOV instruction. Immediate data cannot be moved into a segment register. Immediate data cannot be moved into a segment register. CS cannot successfully be loaded with a segment register MOV. CS cannot successfully be loaded with a segment register MOV.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e PUSH and POP PUSH and POP transfer data to and from the stack. The stack is an area of memory that is reused and grows in size with each PUSH and shrinks in size with each POP. PUSH and POP transfer data to and from the stack. The stack is an area of memory that is reused and grows in size with each PUSH and shrinks in size with each POP. PUSH and POP function with either 16- or 32-bit data. PUSH and POP function with either 16- or 32-bit data. PUSHF (PUSHFD) and POPF (POPFD) save and restore the flags (EFLAGS) PUSHF (PUSHFD) and POPF (POPFD) save and restore the flags (EFLAGS) PUSHA (PUSHAD) and POPA (POPAD) save and restore all the registers PUSHA (PUSHAD) and POPA (POPAD) save and restore all the registers

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Load Segment and Index LDS, LES, LSS, LFG, and LGS allow a segment registers and a pointer to both be loaded from memory. LDS, LES, LSS, LFG, and LGS allow a segment registers and a pointer to both be loaded from memory. LDS BX,BOB ;loads DS and BX with the offset and segment address stored in a 32-bit memory location called BOB.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e LEA The LEA instruction loads the effective address of a memory location into a pointer or index register. The LEA instruction loads the effective address of a memory location into a pointer or index register. At times we do the same operation with a MOV and the keyword OFFSET At times we do the same operation with a MOV and the keyword OFFSET MOV BX,OFFSET FRED LEA BX,FRED Both instruction accomplish the same task.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e String Data Transfer Instructions String data transfer instructions are: LODS, STOS, MOVS, INS, and OUTS. String data transfer instructions are: LODS, STOS, MOVS, INS, and OUTS. These instructions use the direction flag bit to select the way that a pointer is modified after the instruction. D = 0 auto-increment and D = 1 auto-decrement. These instructions use the direction flag bit to select the way that a pointer is modified after the instruction. D = 0 auto-increment and D = 1 auto-decrement. Many of these instructions can be prefixed with a REP (repeat) to repeat the instruction the number of times stored in the CX register. Many of these instructions can be prefixed with a REP (repeat) to repeat the instruction the number of times stored in the CX register.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Miscellaneous NOP (does nothing) NOP (does nothing) XCHG (swaps contents) XCHG (swaps contents) XLAT (table lookup) XLAT (table lookup) CLC, STC, CMC (modify Carry) CLC, STC, CMC (modify Carry) STD and CLD (modify direction) STD and CLD (modify direction) STI and CLI (modify interrupt) STI and CLI (modify interrupt)

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e IN and OUT The two I/O instructions transfer data between an I/O device and the accumulator (AL, AX, and EAX). The two I/O instructions transfer data between an I/O device and the accumulator (AL, AX, and EAX). 16-bit I/O address means there are up to 64K I/O devices possible in a system. 16-bit I/O address means there are up to 64K I/O devices possible in a system.