Functional Coverage Driven Test Generation for Validation of Pipelined Processors P. Mishra and N. Dutt Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Vol. 2, pp. 678 – 683, 2005 Speaker: Wen-Kai Huang

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 2/22 Abstract  Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a functional coverage based test generation technique for pipelined architectures. The proposed methodology makes three important contributions. First, a general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. Second, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, test generation procedures are presented that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate that the number of test programs generated by our approach to obtain a fault coverage is an order of magnitude less than those generated by traditional random or constrained- random test generation techniques.

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 3/22 What’s the Problem  Functional validation of microprocessors is one of the most complex and expensive tasks in SOC design  Code coverage measures are commonly used  Statement coverage  Branch coverage  Condition coverage  Path coverage  FSM coverage  However, these measures do not have any direct relationship to functionality of the device

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 4/22 Related Works  Simulation is the most widely used form Random (constrained-random) test programs Directed test programs  Many techniques have been proposed for automatic generation of test programs [1, 4, 9, 11, 12, 16, 7, 3, 8, 6, 10, 13, 2, 14, 15].  However, these previous works do not  Provide a comprehensive metric to measure the coverage of the pipeline interactions, or  Describe functional fault models for pipelined architectures, use it to define functional coverage

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 5/22 Main Ideas  This paper makes three important contributions  Use general graph-theoretic model to capture the structure and behavior of pipelined processors  Propose a functional fault model for functional coverage measurements  Design an automatic test generation that accept the graph model as input and generate test programs as output

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 6/22 Modeling for Processor Structure  Modeled as a graph  Components  nodes Units (e.g. ALUs) Storages (e.g. register files)  Connectivity  edges Pipeline edges Data transfer edges

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 7/22 Example of Structure Graph

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 8/22 Modeling for Instruction Behavior  Also use the graph model  Fields of each operation  nodes Opcode Argument  Orderings between the fields  edges Syntactical ordering Execution ordering

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 9/22 Example of Behavior Graph

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 10/22 Mapping between Structure and Behavior  unit-to-opcode (opcode-to-unit)  Maps unit nodes in structure graph to opcode nodes in behavior graph  Example  Unit Fetch maps to opcodes {ADD, STORE}  Unit ALU maps to opcode {ADD}  Unit AddrCalc maps to opcode {STORE}

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 11/22 Functional Fault Models  Register Read/Write Model  Operation Execution Model  Execution Path Model  Pipeline Execution Model

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 12/22 Fault Model for Register Read/Write  All registers should be written and read correctly  If V Ri is written in register Ri and read back, the output should be V Ri. In the presence of a fault, output in not equal to V Ri  Coverage Estimation  A fault in this model is covered if the register is written first and read later

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 13/22 Test Generation for Register Read/Write

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 14/22 Fault Model for Operation Execution  All operations must execute correctly  Let val i, where val i = f opcodei (src1,src2,…), denote the result of computing the operation “opecode i dest, src1, src2, …”.  The destination will contain the value val i. Under a fault, the destination is not equal to val i  Coverage Estimation  A fault in this model is covered if the operation is performed, and the result of the computation is read

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 15/22 Test Generation for Operation Execution

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 16/22 Fault Model for Execution Path  Execution Path (ep)  For an operation, the activated pipeline path (pp) with its data-transfer paths (dp)  An execution path ep opi is faulty if it produces incorrect result during execution of operation opi  Coverage Estimation  A fault in this model is covered if the execution path is activated, and the result of the computation is read

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 17/22 Test Generation for Execution Path

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 18/22 Fault Model for Pipeline Execution  A pipeline is faulty if it produces incorrect results due to execution of multiple operations in the pipeline  Stall sets  Exception sets  Pipeline interactions  Coverage Estimation  A fault in this model is covered if the fault is activated due to execution of multiple operations in the pipeline, and the result of the computation is read

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 19/22 Test Generation for Pipeline Execution

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 20/22 Case Study  Apply the proposed methodology on two architectures  VLIW DLX  LEON2 (SPARC V8)  Experimental Setup  Use Specman Elite ‘e’ language to implement executable specification  Use the propsed methodology to generate test programs  Apply the programs on the RTL codes and specifications, and compare the results

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 21/22 Experimental Results

2005/8/22 Functional Coverage Driven Test Generation for Validation of Pipelined Processors 22/22 Conclusions  Functional verification of microprocessors is one of the most complex and expensive tasks in the SOC design process  The three contributions of this paper  A general graph-model for structure and behavior modeling  A functional fault model used in defining the functional coverage  An test generation procedures were presented