© intec 2000 Packaging of parallel optical interconnects modules with on chip optical access François Marion / Julien Routin (LETI) Ronny Bockstaele / Olivier Rits (IMEC)

WORKSHOP, Paris CNIT, February 20, 2003 Summary Packaging for today  Flip chip technology  BGA package  Alignment techniques for fiber connector Packaging for the future CSP package development Flip/chip over glass sheet PCB Packaged CMOS chips with direct on chip optical access DTA Digital technology assessment testbed PCB backplane Optical pathways

WORKSHOP, Paris CNIT, February 20, 2003 Packaging for today Packaging specifications Electrical interface296 I/O’s, LVDS signals Optical interface64 optical in, 64 optical out Mechanical interfacealignment of fiber connector : +/-5µm Thermal interface10W thermal dissipation Hermeticitysemi-hermetic packaging Packaging specifications PACKAGED chip

WORKSHOP, Paris CNIT, February 20, electrical I/Os 64 optical outputs 64 optical inputs Thermal sink 10W +/-5µm mechanical guide Packaging for today Packaging specifications

WORKSHOP, Paris CNIT, February 20, 2003 Packaging for today Packaging specifications

WORKSHOP, Paris CNIT, February 20, 2003 Develop reliable flip-chip technology for direct coupling of large arrays opto-chips on CMOS Provide custom BGA package Provide alignment aids for optical connector passive alignment Packaging for today Packaging specifications DIFFERENT TASKS

WORKSHOP, Paris CNIT, February 20, 2003 Develop flip chip technology : wafer bumping Packaging for today DTA1 CMOS Bumps for glass board F/C Bumped CMOS chip Bumps for opto chips F/C Bumps for silicon benches F/C

WORKSHOP, Paris CNIT, February 20, 2003 Develop flip chip technology : wafer scale hybridization Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 Post-process on CMOS wafer Develop flip chip technology : wafer scale hybridization bench PIN detector VCSEL F/C optos and µbench on DTA1 CMOS Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 CUSTOM BGA PACKAGE Provide BGA package Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 High speed I/O’s (diff pairs) Low speed I/O’s SnPb bumps (302) Provide BGA package Controlled geometry X,Y Z Thermal sink Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 Silicon bench alignement INDEX alignement Develop alignment technique Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 Silicon bench for X,Y,Z alignment Guiding pins +/- 5µm X,Y misalignment versus optos Develop silicon bench alignment technique Packaging for today

WORKSHOP, Paris CNIT, February 20, 2003 Develop silicon bench alignment technique Packaging for today AssemblageIO.exe

WORKSHOP, Paris CNIT, February 20, 2003 INDEX ALIGNMENT Alignment is based on measurement of coordinates, not based on mechanical contact Then attach using UV-curable adhesive Package on ( ,  ) stage Spacer plate on (X,Y,Z,  ) stage CMM measuring head Assembly of the package using index alignment

WORKSHOP, Paris CNIT, February 20, 2003 CSP package New concept -Package size reduced to 15*15mm (vs. 26*28mm for « today BGA ») -Alignment pins placement made easier -NO wirebonds (increased speed) -Optics included in pathway = -connector made easier -optical coupling made easier -hermeticity made easier Packaging for tomorrow CSP package CMOS + optos Direct hybridization of CMOS+opto on customized CSP ceramic To PCBOptics in pathway CSP package

WORKSHOP, Paris CNIT, February 20, 2003 ULTIMATE : direct flip chip over glass sheet PCB Chip on optical (glass sheet) board Packaging for tomorrow Silicon CMOS Electrooptical PCB Glass waveguide Copper traces (Electronic) Optical waveguides (photonic)

WORKSHOP, Paris CNIT, February 20, 2003 CONCLUSION Conclusion : Packaging for to-day = first packaged modules delivered Packaging for tomorrow = development on going: CSP (chip scale packaging) Chip On Board packaging (glass sheet board)