E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon, Nov 10 Analog Simulation for ExtractedRC Secure Electronic Voting Terminal

Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX bit Add/Sub 01 8 bit MUX 16bi t REG 8-bit REG COMMS Register Shift Registe r In Shift Registe r Out constant init

COMMS Layout Complete DRC + LVS Complete ExtractedRC Simulation In Progress Next time: Extracted Simulation

COMMS Full Schematic Components FF 8 bit (2) FF_C 16 bit (1) XOR 8 bit (4) Inv (1) FA 8bit (4) FA 16 bit (1) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4)

COMMS Full Layout 82 by 80

COMMS Simulation

COMMS ExtractedRC Simulation

COMMS ExtractedRC Zoomed

FSM FSMs are complete and working The layout is not finalized and needs to be cleaned The bugs have been removed from the layout and the schematic was updated Exhaustive analog simulations are not complete (waiting for final layout changes)

FSM Simulations The original schematic simulations (No load or impeded input) functioned correctly with only minor transient spikes between states

FSM Simulations Without RC extraction or output loads the layout waveforms looked as clean as the schematic

FSM Simulations The early versions of the unloaded extractedRC layout had very severe glitches on the register outputs

FSM Simulations After changing the configuration of the transistors in the register layout, the final simulations the loaded fsm (extractedRC ) show a better waveform

SRAM Row decoders: Complete and LVSing SRAM layout: Complete and LVSing ExtractedRC Simulation In Progress Next time: More Simulation for ExtractedRC

Decoder ExtractedRC Simulation

SRAM Cell Write ExtratedRC Simulation

FLOORPLAN Updated floorplan based on functional blocks

Old Floorplan ●The aspect ratio 2:1 ●Doubled size in COMMS Block ●The interconnects travel heavily over the FSM ●These are mostly 1 bit enable signals and some are address lines ●The address lines and data bus are buffered

Encryption Key SRAM (4 byte) 2bit Address 8bit Data Machine Initialization FSM 1bit Activate next Data Bus COMMS 1bit Data Ready 8bit Data 1bit Message Message ROM 8bit Data 4-bit Data bus control Machine Initialization FSM

User ID SRAM (8 byte) 3bit Address 8bit Data User ID FSM 1bit Activate next Data Bus COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this 1bit Reactivate this Display 8bit Data 7-bit Data bus control User Input 1bit Yes Signal 1bit No Signal User ID FSM

Choice SRAM (4 byte) 2bit Address 8bit Data User Input 1bit Next Page Signal Selection FSM 1bit Activate next Data Bus 8bit Data COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this 1bit Reactivate this Display 8bit Data 6-bit Data bus control 1bit Previous Page Signal Selection Counter 8bit Data 3bit Count Selection FSM

User Input 1bit Yes Signal Confirmation FSM 1bit Reactivate Selection Data Bus COMMS 1bit Data Ready 8bit Data 2bit Message Message ROM 8bit Data 1bit Activate this Display 8bit Data 8-bit Data bus control 1bit No Signal 1bit Reactivate User ID User ID SRAM (8 byte) 8bit Data Write-in SRAM (64 byte) 8bit Data Choice SRAM (4 byte) 8bit Data 3bit Address 2bit Address 6bit Address 1bit Reset TX_Check 1bit TX_good Confirmation FSM

New Floorplan

●147 by 132 ●The aspect ratio around 1:1 ●Increased size in COMMS Block ●FSM connects to message ROM, selection counter, tx_check directly ●FSM connects to SRAMS via data bus ●The address lines and data bus are buffered as seen with SRAM tri-state buffers ●COMMS only has 4 data_ready bits connected to FSM block

TODO: For Monday:Complete smaller support logic blocks Complete Global interconnects Updated floor plan LVS & Extracted Simulation Whole Chip