CSE241 R1 Verilog.1Kahng & Cichy, UCSD ©2003 CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: Verilog Introduction

CSE241 R1 Verilog.2Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation

CSE241 R1 Verilog.3Kahng & Cichy, UCSD ©2003 Introduction  Learn Verilog basics l Hardware Description Language Semantics l Verilog Syntax l Features  How to use Verilog for behavioral design  How to use Verilog for structural design  How to write Verilog for synthesis (brief)  Examples!

CSE241 R1 Verilog.4Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  General  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation

CSE241 R1 Verilog.5Kahng & Cichy, UCSD ©2003 Introduction - Motivation  Generic HDL uses: l Simulation -Test without build l Synthesis -Real hardware (gates) l Documentation -Self documenting -Portable

CSE241 R1 Verilog.6Kahng & Cichy, UCSD ©2003 HDL vs High Level Languages  HDLs represent: l Electricity -Ultimately a physical entity l Parallelism - Concurrency l Time

CSE241 R1 Verilog.7Kahng & Cichy, UCSD ©2003 Hardware Description Languages  Need a description level up from logic gates.  Work at the level of functional blocks, not logic gates l Complexity of the functional blocks is up to the designer l A functional unit could be an ALU, or could be a microprocessor  The description consists of functions blocks and their interconnections l Describe functional block (not predefined) l Support hierarchical description (function block nesting)  To make sure the specification is correct, make it executable. l Run the functional specification and check what it does Slide courtesy of Ken Yang, UCLA

CSE241 R1 Verilog.8Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Syntax  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Examples

CSE241 R1 Verilog.9Kahng & Cichy, UCSD ©2003 Verilog Naming Conventions  The following must be used in all code: l Two slashes “//” are used to begin single line comments l A slash and asterisk “/*” are used to begin a multiple line comment and an asterisk and slash “*/” are used to end a multiple line comment. l Names can use alphanumeric characters, the underscore “_” character, and the dollar “$” character l Names must begin with an alphabetic letter or the underscore. l Spaces are not allowed within names

CSE241 R1 Verilog.10Kahng & Cichy, UCSD ©2003 Reserved Keywords  The following is a list of the Verilog reserved keywords:

CSE241 R1 Verilog.11Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Examples

CSE241 R1 Verilog.12Kahng & Cichy, UCSD ©2003 Procedural Statements  Control statements l This type of control statement implies sequential ordering keyword always provides functionality of a tiny program that executes sequentially  Inside an always block, can use standard control flow statements: l if ( ) then else ; case ( ) : ; … default: l Case statements are prioritized -The second case entry can’t happen unless the first does not match. -May not be what the actual hardware implies – especially when cases are mutually exclusive. -Need additional directives (parallel-case) to indicate this -Statements can be compound (use begin and end to form blocks)  Example: (Activation List) begin // more than 1 statement allowed inside here if (x==y) then out= in1 else out = in2; end

CSE241 R1 Verilog.13Kahng & Cichy, UCSD ©2003 Module vs. Procedure  Module is a method of building structural hierarchy  Procedure (function) is a method of building behavioral hierarchy

CSE241 R1 Verilog.14Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Examples

CSE241 R1 Verilog.15Kahng & Cichy, UCSD ©2003 Structural Description  Modules l Represent macros l Simulate some wanted function l Can contain hierarchy

CSE241 R1 Verilog.16Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Examples

CSE241 R1 Verilog.17Kahng & Cichy, UCSD ©2003 Behavioral Statements  if-then-else l What you would expect, except that it’s doing 4-valued logic. 1 is interpreted as True; 0, x, and z are interpreted as False  case l What you would expect, except that it’s doing 4-valued logic l If “selector” is 2 bits, there are 4 2 possible case-items to select between l There is no break statement — it is assumed.  Funny constants? l Verilog allows for sized, 4-valued constants l The first number is the number of bits, the letter is the base of the following number that will be converted into the bits. 8’b00x0zx10 if (select == 1) f = in1; elsef = in0; case (selector) 2’b00: a = b + c; 2’b01: q = r + s; 2’bx1: r = 5; default: r = 0; endcase assume f, a, q, and r are registers for this slide Slide courtesy of Don Thomas, Carnegie Mellon

CSE241 R1 Verilog.18Kahng & Cichy, UCSD ©2003 Behavioral Statements  Loops l There are restrictions on using these for synthesis — don’t. l They are mentioned here for use in test modules  Two main ones — for and while l Just like in C l There is also repeat and forever — see the book reg[3:0]testOutput, i; … for (i = 0; i <= 15; i = i + 1) begin testOutput = i; #20; end reg[3:0]testOutput, i; … i = 0; while (i <= 15)) begin testOutput = i; #20 i = i + 1; end Important: Loops must have a delay operator (or as we’ll see later, or wait(FALSE)). Otherwise, the simulator never stops executing them. Slide courtesy of Don Thomas, Carnegie Mellon

CSE241 R1 Verilog.19Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Examples

CSE241 R1 Verilog.20Kahng & Cichy, UCSD ©2003 How to build and test a module  Construct a “test bench” for your design l Develop your hierarchical system within a module that has input and output ports (called “design” here) l Develop a separate module to generate tests for the module (“test”) l Connect these together within another module (“testbench”) module design (a, b, c); input a, b; outputc; … module test (q, r); output q, r; initial begin //drive the outputs with signals … module testbench (); wirel, m, n; designd (l, m, n); test t (l, m); initial begin //monitor and display … Slide courtesy of Don Thomas, Carnegie Mellon

CSE241 R1 Verilog.21Kahng & Cichy, UCSD ©2003 Topic Outline  Introduction  Verilog Background  Signals  Connections  Modules  Procedures  Structural  Behavioral  Testbenches  Simulation  Example  Coding Style

CSE241 R1 Verilog.22Kahng & Cichy, UCSD ©2003 Creating Code  Example: l Given a specification – “build full adder” l Name signals: -Carry in, carry out, A, B

CSE241 R1 Verilog.23Kahng & Cichy, UCSD ©2003 Full-adder Code module full_adder (a1, a2, ci, s, co); //  lists full input/output signal list input a1, a2, ci; //input declaration output sum, co; //output declaration assign s = a1 ^ a2 ^ ci; assign co = (a1 & a2) | (a1 & ci) | (a2 & ci); endmodule Sensitivity List

CSE241 R1 Verilog.24Kahng & Cichy, UCSD ©2003 Another Verilog Example module a (…); reg e; task b; reg c; begin : d reg e; e = 1; a.e = 0; end endtask always begin : f reg g; a.b.d.e = 2; g = q.a.b.d.e; e = 3; end endmodule e’s hierarchical name is …a.b.d.e g’s hierarchical name is …a.f.g named begin-end block some ugliness here… Chapter 2.6 assumes a is instantiated in q Slide courtesy of Don Thomas, Carnegie Mellon