Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory.

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Presentation transcript:

Transmitter for Quantum Encryption System Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman High Speed Digital Systems Laboratory

Background Several methods can be used for encrypting information. One of them is the BB84 scheme, which was developed by Brassard & Bennett. The advantage of this method is that it is impossible to crack it, because it is based on the “No Cloning” principle. The BB84 scheme was mathematically proved as a perfectly safe method.

Project’s Objectives The transmitter module is part of a complex system, which purpose is to send a digital code, which will later be used as key for encrypting and decrypting information. Our goal is to produce an electrical pulse which is 0.5ns wide and its magnitude is 4v. The purpose of this pulse is to activate the laser diode.

Inputs & Outputs Transmitter מקור מתח Trig_StabTrig_Quant (10 nsec) P_StabP_Quant (0.5 nsec) P_SyncRef

The Overall System Block Diagram Computer (Controller) TransmitterReciever Interfrometers, etc. Computer + Counter Synchronization

The Transmitter Block Diagram Pulse triggerD.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber Multiplyer1:2 Balance 2 Unbalance Balance 2 Unbalance Gain P_QuantP_Sync

D.D.LTTL 2 ECL ECL Programmable Delay Chip 1:2 ECL Programmable Delay Chip Long fiber Multiplyer Balance 2 Unbalance Gain P_Stab The Transmitter Block Diagram (Cont.) Pulse trigger

The Transmitter Block Diagram (Cont.) P_StabP_Quant P_Sync Module 1Module 2 FPGA Controllers

Components In our project we will be using components which are implemented in various technologies, such as TTL, ECL, CMOS. Therefore, it is important to check the technological compatibility of all the components we use. Some of these components are: DDL (Digital Delay Line), TTL 2 ECL, Balance 2 Unbalance, Amplifier, etc.

Schedule By 2.5 – Final block diagram approved by the supervisor. By 11.5 – Final Components list + ordering the needed components. By 20.5 – Full Orcad scheme. (Mid-term presentation)