Spring 07, Mar 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 A Linear Programming Solution to Clock Constraint.

Slides:

Advertisements

Similar presentations

CS 140 Lecture 11 Sequential Networks: Timing and Retiming Professor CK Cheng CSE Dept. UC San Diego 1.

Advertisements

Spring 08, Mar 11 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Zero - Skew Clock Routing Vishwani D. Agrawal.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Performance analysis of sequential machines.

1 KU College of Engineering Elec 204: Digital Systems Design Lecture 12 Basic (NAND) S – R Latch “Cross-Coupling” two NAND gates gives the S -R Latch:

Leakage and Dynamic Glitch Power Minimization Using MIP for V th Assignment and Path Balancing Yuanlin Lu and Vishwani D. Agrawal Auburn University ECE.

Yuanlin Lu Intel Corporation, Folsom, CA Vishwani D. Agrawal

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University,

Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.

Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2012 Power and Ground Vishwani D. Agrawal James J.

Spring 07, Apr 10, 12 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Constraint Graph and Performance Optimization.

Spring 07, Feb 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Verification Vishwani D. Agrawal James J. Danaher.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering.

ENGIN112 L28: Timing Analysis November 7, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis.

1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

Spring 08, Apr 1 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Testability Measures Vishwani D. Agrawal James.

9/08/05ELEC / Lecture 51 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Spring 08, Jan 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

Spring 08, Jan 31.. ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Timing Simulation and STA Vishwani D. Agrawal.

Spring 07, Jan 16 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Introduction Vishwani D. Agrawal James J. Danaher.

9/20/05ELEC / Lecture 81 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Retiming Vishwani D. Agrawal James J. Danaher.

Spring 07, Feb 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory Vishwani D. Agrawal.

Spring 07, Jan 23 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Moore’s Law Vishwani D. Agrawal James J. Danaher.

May 28, 2003Minimum Dynamic Power CMOS1 Minimum Dynamic Power CMOS Circuits Vishwani D. Agrawal Rutgers University, Dept. of ECE Piscataway, NJ 08854

Spring 07, Mar 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Verification and Optimization Vishwani D.

Vishwani D. Agrawal James J. Danaher Professor

Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.

Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Constraint Graph and Performance Optimization.

Fall 2006, Sep. 26, Oct. 3 ELEC / Lecture 7 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Dynamic Power:

Spring 07, Apr 5 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Retiming Vishwani D. Agrawal James J. Danaher Professor.

Fall 06, Sep 14 ELEC / Lecture 5 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits (Formerly ELEC / )

Spring 07, Mar 1, 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Timing Simulation and STA Vishwani D. Agrawal.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 6 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing Vishwani.

Chapter #6: Sequential Logic Design 6.2 Timing Methodologies

Spring 08, Feb 26 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew Problem Vishwani D. Agrawal James J.

Spring 08, Feb 6 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Timing Verification and Optimization Vishwani D.

CS 151 Digital Systems Design Lecture 28 Timing Analysis.

Spring 07, Feb 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Power Dissipation in VLSI Chips Vishwani D. Agrawal.

Spring 2010, Feb 10...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Constraint Graph and Retiming Solution Vishwani.

DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING BARIS TASKIN and IVAN S. KOURTEV ISPD 2005 High Performance Integrated Circuit Design Lab. Department of.

ELEC 7770 Advanced VLSI Design Spring 2014 Timing Simulation and STA Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University,

Spring 2014, Feb 14...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Constraint Graph and Retiming Solution Vishwani.

Spring 2010, Mar 10ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing Vishwani D. Agrawal James J. Danaher.

Spring 2014, Mar 17...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Zero - Skew Clock Routing Vishwani D. Agrawal.

Prof. Joongho Choi CMOS SEQUENTIAL CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul.

1 COMP541 Sequential Logic Timing Montek Singh Sep 30, 2015.

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

ELEC Digital Logic Circuits Fall 2014 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

ELEC 7770 Advanced VLSI Design Spring Gate Delay and Circuit Timing

ELEC 7770 Advanced VLSI Design Spring 2016 Introduction

Vishwani D. Agrawal James J. Danaher Professor

ELEC 7770 Advanced VLSI Design Spring 2016 Clock Skew Problem

ELEC 7770 Advanced VLSI Design Spring 2016 Zero-Skew Clock Routing

ELEC 7770 Advanced VLSI Design Spring 2012 Clock Skew Problem

ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem

ELEC 7770 Advanced VLSI Design Spring 2012 Retiming

Vishwani D. Agrawal James J. Danaher Professor

ELEC 7770 Advanced VLSI Design Spring 2010 Interconnects and Crosstalk

Vishwani D. Agrawal James J. Danaher Professor

Pre-Computed Asynchronous Scan Invited Talk

ELEC 7770 Advanced VLSI Design Spring 2014 Technology Mapping

ELEC 7770 Advanced VLSI Design Spring 2016 Technology Mapping

Vishwani D. Agrawal James J. Danaher Professor

Vishwani D. Agrawal James J. Danaher Professor

ELEC 7770 Advanced VLSI Design Spring 2016 Retiming

Timing Analysis and Optimization of Sequential Circuits

ELEC 7770 Advanced VLSI Design Spring 2012 Timing Simulation and STA

ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing

ELEC 7770 Advanced VLSI Design Spring 2010 Zero-Skew Clock Routing

Presentation transcript:

Spring 07, Mar 20 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 A Linear Programming Solution to Clock Constraint Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)2 A General Sequential Circuit Combinational Logic Registers Clock InputsOutputs

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)3 A Level-Sensitive Latch D CK Q QN Clock period, Tck CK time Latch openLatch closedLatch open

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)4 Alternative Implementation D CK Q J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Wiley Interscience, 2004, p.137.

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)5 Data Must be Stable Before Latch Closes D = 0 → 1 CK = 1 → 0 Q QN Clock period, Tck CK time Latch openLatch closed 0→1→0→0→ 1→1→0→0→ 0→0→1→0→1→ 1→0→1→0→1→ Unstable state Stable data delays

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)6 Data and Clock Parameters Clock period, Tck CK time Latch openLatch closed D time Stable data Stable Q Q time Setup time Hold time CK-to-Q delay

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)7 Design With Level-Sensitive Latches Comb. Logic Level-sens. Latches PI PO Comb. Logic Level-sens. Latches PI PO CK

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)8 Edge-Triggered Flip-flop D CK Q QN Clock period, Tck CK time Master openSlave open Master latchSlave latch Trigger edges Setup time Hold time CK-to-Q

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)9 A Dynamic Implementation D Q CK VDD GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 229.

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)10 A Static Implementation D Q CK VDD GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 230.

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)11 Design With Edge-Triggered Flip-Flops Combinational Logic Flip-flops Clock InputsOutputs

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)12 Setup Time Constraint FF iFF j Combinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j) TsiThi Tqi Clock edge time Tck Tsj Constraint:Tqi + Δ(i,j)≤Tck – Tsj i.e., Δ(i,j)≤Tck – Tsj – Tqi This is known as long path constraint. Note: All times for a FF should be adjusted by its clock skew.

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)13 Hold Time Constraint FF iFF j Combinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j) TsiThi Tqi Clock edge time Tck Tsj Constraint:Tqi + δ(i,j)≥Thj i.e., δ(i,j)≥Thj – Tqi Thj This is known as short path constraint. Note: All times for a FF should be adjusted by its clock skew.

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)14 Solving Hold Time Problem (1) PO (FFi) PO (FFj) PI (FFi) PI (FFj) PO PI Fanout node Internal edges (fixed delays) External edges (variable delays)

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)15 Solving Hold Time Problem (2)  Variables:  Earliest arrival time at node i = ai  Longest arrival time at node i = Ai  Buffer delays on external edge (i,j) = wij  Constants:  At PI i: Ai = Λi and ai = λi, user specified.  At PI (FF) i: Ai = ai = Tqi

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)16 Solving Hold Time Problem (3)  Constraints:  At PO i: Ai ≤ Ri and ai ≥ ri, user defined.  At PO (FF) i:  ai ≥ Thi, short path constraint.  Ai ≤ Tck – Tsi, long path constraint.  Optimization function (a linear approximation to minimum number of delay buffers): minimize ∑ wij all external edges (i,j)

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)17 Linear Programming Solution (1) minimize ∑ wij all external edges (i,j) Subject to:Aj ≥ Ai + wijfor all i ε Fanin(j) aj ≤ ai + wijfor all i ε Fanin(j) Ai ≤ Rifor all i ε PO ai ≥ rifor all i ε PO Ai ≤ Tck – Tsi for all i ε PO(FF i) ai ≥ Thi for all i ε PO(FF i) Ai = Λifor all i ε PI ai = λifor all i ε PI Ai = Tqifor all i ε PI(FF i) ai = Tqi for all i ε PI(FF i)

Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)18 Linear Programming Solution (2)  Solution inserts smallest delays in interconnects to satisfy short path constraints.  Maintains the specified clock period and satisfies setup time constraints. Reference:N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.