Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans.

Slides:



Advertisements
Similar presentations
Uli Schäfer Trigger Status JEP (JET/ENERGY PROCESSOR) Komponenten JEM0 (JET/ENERGY MODULE) -Hardware -Firmware JEM1 nächste Tests / Termine Production.
Advertisements

GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
System Design GroupInstrumentationViraj PereraRAL2-March-01 Prototype ROD Prototype ROD (6U VME) – Requirements 4 channel (CPMs) prototype Perform zero.
Uli Schäfer JEM Status and Test Results Hardware status JEM0 Hardware status JEM1 RAL test results.
Uli Schäfer JEM Status and plans Hardware status JEM0 Hardware status JEM1 Plans.
5th April, 2005JEM FDR1 JEM FDR: Design and Implementation JEP system requirements Architecture Modularity Data Formats Data Flow Challenges : Latency.
GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
Programmable logic devices / tools Programmable logic devices are digital logic devices, providing combinatorial logic (gates, look-up tables) and flip-flops.
GOLD Status and Phase-1 Plans Andi E. & Uli S. Uli Schäfer 1.
Uli Schäfer 1 BLT – status – plans BLT – backplane and link tester Recent backplane test results Test plans – week June 15.
Phase-0 topological processor Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.
Level-1 Topology Processor for Phase 0/1 - Hardware Studies and Plans - Uli Schäfer Johannes Gutenberg-Universität Mainz Uli Schäfer 1.
JEM upgrades and optical data transmission to FEX for Phase 1 Andi E. & Uli S. Uli Schäfer 1.
Uli Schäfer 1 (Not just) Backplane transmission options Upgrade will always be in 5 years time.
Uli Schäfer 1 Mainz L1Calo upgrade activities news – BLT hardware/firmware status.
Uli Schäfer. Electronic Design Software: Status / Requirements A) Europractice subscription: 200/500/900 €/y for Xilinx donation/full/IC + Maintenance:
Cluster Processor Module : Status, test progress and plan Joint Meeting, Mainz, March 2003.
Uli Schäfer JEM Plans Status (summary) Further standalone tests Sub-slice test programme JEM re-design Slice test.
Uli Schäfer JEM0 Status (summary) 3 JEM0s up and running: JEM0.0 used for standalone tests only (Mainz) JEM0.1 fully qualified module0 JEM0.2 (like JEM0.1.
Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans.
Uli Schäfer 1 JEM PRR Design changes Post-FDR tests FDR issues.
Uli Schäfer JEM0 JEM0 Hardware : overview, history, and status JEM0 Firmware : algorithms, status JEM - The next iteration : many questions, few answers.
5th April, 2005JEM FDR1 Energy Sum Algorithm In all stages saturate outputs if input is saturated or arithmetic overflow occurs Operate on 40Mb/s data.
Uli Schäfer JEM0 hardware history and status JEM - The next iteration : many questions, few answers test plans and time scale.
Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans.
Uli Schäfer JEM0 (*) JEM0 Hardware : overview, history, and status JEM0 Firmware : algorithms, status JEM – plans and timescale (*) Module0 specifications.
Uli Schäfer 1 JEM: Status and plans Pre-Production modules Status Plans.
Uli Schäfer JEM Status and plans Firmware -Algorithms -Tools -Status Hardware -JEM1 -Status Plans.
Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.
Uli Schäfer 1 JEM1: Status and plans JEM1.1 Status Plans.
5th April, 2005JEM FDR1 JEM FDR: Design and Implementation JEP system requirements Architecture Modularity Data Formats Data Flow Challenges : Latency.
Uli Schäfer 1 CP/JEP backplane test module What’s the maximum data rate into the S-CMM for phase-1 upgrade ?
Uli Schäfer 1 Production modules Status Plans JEM: Status and plans.
Target Control Electronics Upgrade 08/01/2009 J. Leaver P. Smith.
Hardware status GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
Uli Schäfer 1 JEM Test Strategies Current plan: no JTAG tests at R&S  initial tests done at MZ Power-up / currents Connectivity tests (JTAG) per (daughter)
Uli Schäfer JEM Status and plans RAL test results Hardware status Firmware Plans.
Uli Schäfer JEM1 In input modules T,S probably mix of φ-bins 5,6 due to routing problems of high-speed LVDS links With current algorithm rounding errors.
Uli Schäfer JEM hardware / test JEM0 test programme Mainz standalone RAL sub-slice test JEM re-design Heidelberg slice test.
Uli Schäfer 1 Production and QA issues Design Modules have been designed, with schematic capture and layout, in Mainz (B.Bauss) Cadence design tools, data.
Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.
Uli Schäfer JEM Status and plans Firmware Hardware status JEM1 Plans.
Uli Schäfer 1 JEM: Status and plans Production / commissioning Plans.
Uli Schäfer JEM Status and plans Algorithms Hardware JEM0, JEM1 Tests Plans.
Uli Schäfer 1 Production modules Status Plans JEM: Status and plans.
Status and planning of the CMX Philippe Laurens for the MSU group Level-1 Calorimeter Trigger General Meeting, CERN May 24, 2012.
JEP HW status and FW integration plans Uli Schaefer and Pawel Plucinski Johannes-Gutenberg Universitaet Mainz Stockholm University.
Topology System Uli Schäfer 1 B.Bauß, V.Büscher, W.Ji, U.Schäfer, A.Reiß, E.Simioni, S.Tapprogge, V.Wenzel.
L1Topo Status & Plans Uli Schäfer 1 B.Bauß, V.Büscher, W.Ji, S.Krause, S.Moritz, U.Schäfer, A.Reiß, E.Simioni, S.Tapprogge, V.Wenzel.
Hardware status GOLD Generic Opto Link Demonstrator Assess the use of optical backplane connectivity for use on L1Calo Uli Schäfer 1.
Uli Schäfer 1 JEM configurator progress FPGAs are RAM-based programmable logic devices Need to be loaded with a ‘configuration’ after power-up, so as to.
L1Topo-phase0 Uli Schäfer 1. Topo GOLD successfully used to explore technologies and initially verify 6.4Gb/s link integrity over moderate length electrical.
Gueorgui ANTCHEVPrague 3-7 September The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment G. Antchev a, b, P. Aspell.
Uli Schäfer 1 JEM Status and plans Hardware -JEM1 -Status Firmware -Algorithms -Status Plans.
Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.
FED Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided.
ATLAS Trigger / current L1Calo Uli Schäfer 1 Jet/Energy module calo µ CTP L1.
16th July 2003Tracker WeekJohn Coughlan et. al.FED-UK Group Final FED Progress Report CMS Tracker Week 16th July 2003.
Samuel Silverstein Stockholm University CMM++ firmware development Backplane formats (update) CMM++ firmware.
ZPD Project Overview B A B AR L1 DCT Upgrade FDR Masahiro Morii Harvard University Design Overview Progress and Changes since CDR Current Status Plans.
Hardware status GOLD Generic Opto Link Demonstrator Uli Schäfer 1.
JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Some VHDL tips.
L1Topo post review Uli Schäfer 1 Observations, options, effort, plans Uli.
GOLD TESTS (Virtex-6) ● Jitter analysis on cleaned TTC clock ( σ = 2.9 ps) ● Signal integrity: sampled in several positions along the chain ● MGT and o/e.
Uli Schäfer 1 Mainz R&D activities. Uli Schäfer 2 MZ R&D BLT has been built and tested (backplane transmission only). A few minor issues were found. Possible.
ATLAS calorimeter and topological trigger upgrades for Phase 1
A New Clock Distribution/Topology Processor Module for KOTO (CDT)
Generic Opto Link Demonstrator
Implementation of the Jet Algorithm ATLAS Level-1 Calorimeter Trigger
CPM plans: the short, the medium and the long
Presentation transcript:

Uli Schäfer 1 JEM1: Status and plans Hardware status Firmware status Plans

Uli Schäfer 2 JEM1 16 x 6-channel de- serialisers : SCAN on 4 Input daughter modules w. XC2V1500. G-link / Opto daughter module Jet and Sum Processors XC2V2000 (BF package). Configuration : SystemACE 88 pair VMEVME each 165 pins FIO 60 80Mb/s TTCdec CAN System ACE 3 x Mb/s DES Input 2 B 1 A 0 V Input 5 E 4 D 3 C Input 8 H 7 G 6 F Input X 9 W DAQ/Timing/VME To JMM G G Jet R S T U Sum DAQ To SMM ROI Opto clock mirror

Uli Schäfer 3 JEM1 H/W Status Input daughters: 4 modules available 2 fully working (PCB ageing problems) Main board: 1 module available Fully working. Few bug fixes required (2 tracks missing, 1 pull-up). CAN under test. Compatibility ? Flash configurator not yet successfully operated (cfg read error) G-link daughters: 1 (electrical) module available, in-house assembled, re- worked after RAL test. fully (?) working

Uli Schäfer 4 JEM1 firmware status (energy sum / control) Previous JEM0 functionality fully implemented Latency reduction (energy path) ~3 ticks TTCdec : I2C control added TTCrx ID via GeoAdd short broadcast support CPM-style spy memory control (continuous spy, wrap at 255) Playback / spy VME-controlled, use broadcast to reset pointers Flash configurator (ACE) mapped into VME VME control (including configuration) faster and more reliable To be done: Support for CAN (?)

Uli Schäfer 5 Plans : JEM1 Prototype production Make a total of 4 JEMs for slice test & beam test Main board: 3 PCBs available Components available Assembly at Rohde & Schwarz starting next week (?) Input daughter modules (+16): Active components (LVDS/Xilinx) available Slot for PCB production & assembly at Rohde & Schwarz: ? G-link daughter modules: Components available Slot for PCB production & assembly at Rohde & Schwarz: ? Total of four JEMs available for tests early August