Chapter 9 Counters 計數器 Asynchronous Counter Operation 非同步式計數器的運作

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Chapter 9 Counters 計數器 Asynchronous Counter Operation 非同步式計數器的運作 Up/Down Synchronous Counters 上 / 下數的同步式計數器 Design of Synchronous Counters 同步式計數器的設計 Cascaded Counters 串接計數器 Counter Decoding 計數器的解碼 Counter Applications 計數器的應用 Troubleshooting 檢修 Logical Symbols with Dependency Notation 具有相依註標的邏輯符號 Programmable Logic 可程式邏輯 Digital System Application 數位系統的應用

除法器 J K Clk Q Q0 1 Flip-Flop Applications 正反器的用途 Q0 不變 1 Reset Set 轉態 Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--1 A 2-bit asynchronous binary counter. 1. 非同步式計數器的運作 Figure 9--1 A 2-bit asynchronous binary counter. 1 1 1 1 Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作 Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作 Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作例題9-1 如圖9-5所示為一個4位元的非同步二進制計數器, 每一個正反器都是負緣觸發而且有一個10ns的極際延遲時間. (1)設計各正反器輸出的時序圖, (2)算出從Clock輸入加訊號進去到Q3輸出的延遲時間, (3)算出最高工作頻率. Sol: (2) tp(Total) = 4 x 10ns = 40ns (3) fmax = 1/ tp(Total) = 1/40ns = 25MHz Figure 9--5 Four-bit asynchronous binary counter and its timing diagram. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作 Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題9-2 證明一個非同步的計數器如何除12, 從二進制的0000算到1011. 1. 非同步式計數器的運作 Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling. 很尖銳的脈波例題9-2 證明一個非同步的計數器如何除12, 從二進制的0000算到1011. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作 FigureA--21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

1. 非同步式計數器的運作 Figure A--22 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure A-23 74LS93A connected as a modulus-12 counter. 1. 非同步式計數器的運作例題9-3 證明74LS93A 如何作為一個除12的計數器. Figure A-23 74LS93A connected as a modulus-12 counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

A 2-bit synchronous binary counter. 2. 同步式計數器的運作 A 2-bit synchronous binary counter. Figure 9--10 Timing diagram for the counter of Figure 9-11. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

解釋前一頁每次Clock來時Q0及Q1的變化 2. 同步式計數器的運作解釋前一頁每次Clock來時Q0及Q1的變化第一個脈波第二個脈波第三個脈波第四個脈波 Figure 9--9 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--11 A 3-bit synchronous binary counter. 2. 同步式計數器的運作 Figure 9--11 A 3-bit synchronous binary counter. Figure 9--12 Timing diagram for the counter of Figure 9-14. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

2. 同步式計數器的運作 FF2在Q0Q1同時為1時,下一個脈波來會改變狀態, FF3則在Q0Q1Q2同時為1時,下一個脈波來才會改變狀態, Figure 9--13 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--14 A synchronous BCD decade counter.. 2. 同步式計數器的運作 Figure 9--14 A synchronous BCD decade counter.. Figure 9--15 Timing diagram for the BCD decade counter (Q0 is the LSB). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

2. 同步式計數器的運作 Figure A--24 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure A--25 Timing example for a 74HC163. 2. 同步式計數器的運作 Figure A--25 Timing example for a 74HC163. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

2. 同步式計數器的運作 Figure A--26 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure A--27 Timing example for a 74LS160. 2. 同步式計數器的運作 Figure A--27 Timing example for a 74LS160. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--16 A basic 3-bit up/down synchronous counter. 3. 上 / 下數的同步式計數器 Figure 9--16 A basic 3-bit up/down synchronous counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3. 上 / 下數的同步式計數器 Figure 9--17 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure A--28 The 74HC190 up/down synchronous decade counter. 3. 上 / 下數的同步式計數器 Figure A--28 The 74HC190 up/down synchronous decade counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure A--29 Timing example for a 74HC190. 3. 上 / 下數的同步式計數器 Figure A--29 Timing example for a 74HC190. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--18 General clocked sequential circuit. 4. 同步式計數器的設計激勵線輸入線與狀態變數線加到組合邏輯電路產生激勵訊號線狀態變數線 Previous State  Present State  Next State Figure 9--18 General clocked sequential circuit. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--19 State diagram for a 3-bit Gray code counter. 4. 同步式計數器的設計步驟一: 畫出狀態圖 Figure 9--19 State diagram for a 3-bit Gray code counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

步驟四: 根據下一狀態表及正反器的暫態表填寫卡諾圖. 4. 同步式計數器的設計步驟二: 寫出下一狀態表. 步驟三: 寫出正反器的暫態表. 步驟四: 根據下一狀態表及正反器的暫態表填寫卡諾圖. Figure 9--20 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--21 Karnaugh maps for present-state J and K inputs. 4. 同步式計數器的設計 Figure 9--21 Karnaugh maps for present-state J and K inputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--22 Three-bit Gray code counter. 4. 同步式計數器的設計步驟五: 寫出各正反器的輸入端之邏輯表示式 J0 = Q2Q1 + Q2Q1 = Q2 xor Q1 K0 = Q2Q1 + Q2Q1 = Q2 xor Q1 J1 = Q2Q0 K1 = Q2Q0 J2 = Q1Q0 K2 = Q1Q0 Figure 9--22 Three-bit Gray code counter. 步驟六: 畫出電路圖 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題9-5 使用JK正反器, 設計一個如圖9-32所示不按照二進制計數順序的計數器. 4. 同步式計數器的設計 Present State Q2 Q1 Q0 Next State 0 0 1 0 1 0 1 0 1 1 1 1 例題9-5 使用JK正反器, 設計一個如圖9-32所示不按照二進制計數順序的計數器. Figure 9--23 Output Transitions QN QN+1 Flip-Flop Inputs J K 0  0 0 x 0  1 1 x 1  0 x 1 1  1 x 0 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

4. 同步式計數器的設計 Figure 9--24 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

4. 同步式計數器的設計 J0 = 1, K = Q2 J1 = K1 = 1 J2 = K2 = Q1 Figure 9--25 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--26 State diagram for a 3-bit up/down Gray code counter. 4. 同步式計數器的設計例題9-6 試設計一個3位元的格雷碼同步式上下數計數器, 當UP/DOWN為1時往上數, 為0時往下數. Figure 9--26 State diagram for a 3-bit up/down Gray code counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

4. 同步式計數器的設計 Present State Next State Y=0(Down) Y=1(Up) Q2 Q1 Q0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 Output Transitions QN QN+1 Flip-Flop Inputs J K 0  0 0 x 0  1 1 x 1  0 x 1 1  1 x 0

4. 同步式計數器的設計 Figure 9--27 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--28 Three-bit up/down Gray code counter. 4. 同步式計數器的設計步驟五: 寫出各正反器的輸入端之邏輯表示式步驟六: 畫出電路圖 Figure 9--28 Three-bit up/down Gray code counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--29 Two cascaded counters (all J and K inputs are HIGH). 5. 串接計數器 Figure 9--29 Two cascaded counters (all J and K inputs are HIGH). Figure 9--30 Timing diagram for the cascaded counter configuration of Figure 9-38. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--31 A modulus-100 counter using two cascaded decade counters. 5. 串接計數器 Figure 9--31 A modulus-100 counter using two cascaded decade counters. Figure 9--32 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

5. 串接計數器例題9-7 試算出圖9-42中兩個電路全部各除多少? Sol: 9-42(a) 8 x 12 x 16 = 1536 9-42(b) 10 x 4 x 7 x 5 = 1400 Figure 9--33 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題9-8 使用74LS160 計數器設計一個電路, 將1MHz的訊號從Clock端輸入, 輸出端得到10KHz. 5. 串接計數器例題9-8 使用74LS160 計數器設計一個電路, 將1MHz的訊號從Clock端輸入, 輸出端得到10KHz. Figure 9--34 A divide-by-100 counter using two 74LS160 decade counters. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

5. 串接計數器從63C0算到FFFF, 即除以40,000. 63C0H = 25,536. 40,000 = 65535 – 25536 + 1 Figure 9--35 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

解題步驟 (n,m,x,y 皆為正整數) 決定所需位元數 n （x:所需除數）決定所需74161個數 m 畫電路圖

計數器之解碼對計數器序列中任何指定狀態實作其解碼邏輯使用閃控法（Strobe）消除解碼時的脈衝干擾 6. 計數器的解碼 Output=1 解碼器 Output=1 At counter = 6

Figure 9--36 Decoding of state 6 (110). 6. 計數器的解碼 Figure 9--36 Decoding of state 6 (110). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

6. 計數器的解碼 Figure 9--37 A 3-bit counter with active-HIGH decoding of count 2 and count 7. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--38 A basic decade (BCD) counter and decoder. 6. 計數器的解碼 Figure 9--38 A basic decade (BCD) counter and decoder. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

6. 計數器的解碼 Decoding Glitches Figure 9--39 Outputs with glitches from the decoder in Figure 9-38. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

6. 計數器的解碼 Figure 9--40 The basic decade counter and decoder with strobing to eliminate glitches. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--41 Strobed decoder outputs for the circuit of Figure 9-49. 6. 計數器的解碼 Figure 9--41 Strobed decoder outputs for the circuit of Figure 9-49. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. 計數器的應用 Figure 9--42 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-53. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. 計數器的應用 Figure 9--43 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. 計數器的應用 Figure 9--44 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--45 Functional block diagram for parking garage control. 7. 計數器的應用車輛停車控制: 最多可停100輛, 當停滿100輛時指示燈亮起, 同時柵欄放下, 當不滿100輛時指示燈滅掉, 同時柵欄收起. Figure 9--45 Functional block diagram for parking garage control. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. 計數器的應用車輛停車控制 Figure 9--46 Logic diagram for modulus-100 up/down counter for automobile parking control. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--47 Parallel-to-serial data conversion logic. 7. 計數器的應用 Figure 9--47 Parallel-to-serial data conversion logic. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

7. 計數器的應用 Figure 9--48 Example of parallel-to-serial conversion timing for the circuit in Figure 9-47.

8. 檢修 Figure 9--49 Example of a failure that affects following counters in a cascaded arrangement. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

8. 檢修 Figure 9--50 Example of a failure in a cascaded counter with a truncated sequence. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題9-10 分析圖9-60測量的結果是否正確, 如果不正確, 那錯在哪裡? 8. 檢修例題9-10 分析圖9-60測量的結果是否正確, 如果不正確, 那錯在哪裡? Sol: Truncated modulus = full modulus – preset modulus = 164 - 82C016 = 65536 -32472 = 32064 The correct frequency = 10MHz / 32064 = 311.88Hz Modulus = fin / fout = 10MHz / 637.76Hz = 15680 Truncated modulus = full modulus – preset modulus = 65536 – 15680 = 49856 = C2C016 比較 82C016 與 C2C016 就知道錯在哪裡了. Thomas L. Floyd Digital Fundamentals, 8e Figure 9--51 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Q2正確的波形應為紅線的波形, 所以若Q2的波形像綠線的部分則Q2的波形是錯的. 8. 檢修例題9-11 觀察圖9-61的波形看計數器是否正確? Sol: Q2正確的波形應為紅線的波形, 所以若Q2的波形像綠線的部分則Q2的波形是錯的. 仔細比較Q1及Q2的波形, 發現兩者一樣, 會發生這種情況, 可能是AND 下半部內部斷線, 相當於接HIGH, 因此AND Gate 等於沒有作用所致. Figure 9--52 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 9--53 The 74HC163 4-bit synchronous counter. 9. 具有相依註標的邏輯符號 Figure 9--53 The 74HC163 4-bit synchronous counter. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.