On Sub-optimality and Scalability of Logic Synthesis Tools Igor L. Markov and Jarrod A. Roy Dept. of EECS, University of Michigan at Ann Arbor

Outline Motivation and Previous Work Results on Common Problems Primality Testing as a Benchmark Theoretical Bounds Empirical Results Polynomial Fitting Conclusions and Further Work

Quantifyng Scalability Previous work has been in physical design L. Hagen, J.H.Huang, and A.B.Kahng, “Quantified Suboptimality of VLSI Layout Heuristics”, DAC 1995, pp Test cases with optimal cost grow linearly with problem size C.C.Chang, J.Cong, and M.Xie, “Optimality and Scalability Study of Existing Placement Algorithms,” ASP DAC 2003, pp Placement Examples with Known Optima (PEKO) - rather artificial circuits (no long wires) Show a 2x sub-optimality in placement tools Our interest: logic synthesis

Our Work Evaluate scalability of ESPRESSO, SIS, BDS Introduce primality testing as a scalable benchmark for synthesis tools  poly-sized circuits; we derive an upper bound No such poly-sized circuits actually known Show exponential sub-optimality (pessimistic) Multipliers not a problem – can be instantiated

Results on Common Tasks Parity ESPRESSO & SIS: circuits as big as input truth tables BDS: circuits grow linearly Addition ESPRESSO & SIS: work on up to 7(8)-bit adders ~polynomial circuit growth BDS crashes on all inputs (but not immediately) Multiplication ESPRESSO & SIS: work on up to 4(8)-bit multipliers super-polynomial circuits growth BDS crashed on all but the 2-bit multiplier

Log-Log Plot for Adders Poly  Straight Line

Log-Log Plot of Multipliers

Primality Testing AKS algorithm (Agrawal, Kayal & Saxena) “PRIMES is in P”, preprint, August st deterministic poly-time algorithm for primality testing Runs in O*(n 12 ) time for n-bit integers on a RAM machine For 1-tape Turing machine: our bound is O(n 26 ) Well-known result in Complexity Theory implies that combinational circuits of size O(n 52 ) exist The Sophie Germain conjecture, if true, reduces the circuit size bound to O(n 24 ) “True for practical purposes” (verified up to astronomic n)

Results ESPRESSO-exact: runs out of steam at 19 bits SIS (best of full_simplify & script rugged ) Runs out of steam at 20 bits, but otherwise results no better than those for ESPRESSO BDS: runs out of steam at 7 bits No better than SIS or ESPRESSO Super-linear trends in log-log plots suggest exponential growth in circuit size

Log-Log Plot of Espresso Results Known Exponential

Log-Log Plot of SIS Results

Log-Log Plot of BDS Results

Fitting Polynomials to the data Too few data points to see if the trend fits a 24 th degree polynomial We fit the Espresso and SIS data to smaller degree polynomials (up to 18 th ) 13 th -15 th degree were most reasonable for Espresso 13 th -16 th degree were most reasonable for SIS Several characteristics of the fits suggest circuit size growth is exponential

Properties of Good Poly-Fits Monotonically increasing Most coefficients should be positive Leading coefficient must be positive Increased degree should improve fit Behavior outside data region should be reasonable

Polynomial Fitting Espresso Data

Polynomial Fitting SIS Data

Conclusions and Further Work Primality testing appears to expose an exponential sub-optimality in synthesis tools Continued work with primality testing Try new tools: M31, etc. Derive better bounds on circuit size Use more sophisticated algorithms like Fast Fourier multiplication Factor in improvements to AKS Build primality testing circuits in a VHDL, synthesize, see how well they scale Work beyond primality testing Scalability studies based on doubling constructions in the spirit of Hagen et. Al.