Copyright © 2001 Stephen A. Edwards All rights reserved Esterel and Other Projects Prof. Stephen A. Edwards Columbia University, New York

Copyright © 2001 Stephen A. Edwards All rights reserved Outline  Part 1 The Esterel language My compiler for it (DAC 2000)  Part 2 New Esterel Compiler Infrastructure Other projects

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language emit B; emit B; if C emit D; if C emit D; Force signal B to be present in this cycle Emit D if signal C is present

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause Wait for next cycle with A present Wait for next cycle

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end Infinite loop

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end end Run concurrently

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end end Same-cycle bidirectional communication

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Restart when RESET present

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Good for hierarchical FSMs

Copyright © 2001 Stephen A. Edwards All rights reserved The Esterel Language every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Bad at manipulating data

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Esterel Concurrent Control-Flow Graph Step 1: Translate

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Esterel Concurrent Control-Flow Graph Step 1: Translate Scheduled CCFG Step 2: Schedule

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Esterel Concurrent Control-Flow Graph Scheduled CCFG Step 1: Translate Step 2: Schedule Sequential Control-Flow Graph Step 3: Sequentialize

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Esterel Concurrent Control-Flow Graph Scheduled CCFG Sequential Control-Flow Graph Step 1: Translate Step 2: Schedule Step 3: Sequentialize Void foo() { switch (st) { switch (st) { 0: if (IN=3) 0: if (IN=3) st = 5; st = 5; goto L5; goto L5; 1: if (RES) 1: if (RES) st = 3; st = 3; goto L8; goto L8; } L5: switch L5: switch} C Step 4: Generate C

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Void foo() { switch (st) { switch (st) { 0: if (IN=3) 0: if (IN=3) st = 5; st = 5; goto L5; goto L5; 1: if (RES) 1: if (RES) st = 3; st = 3; goto L8; goto L8; } L5: switch L5: switch} Esterel C  Generated code is 2 to 100  faster  1/2 to 1  the size

Copyright © 2001 Stephen A. Edwards All rights reserved The New Compiler every RESET do loop loop await A; await A; emit B; emit B; if C emit D; if C emit D; pause pause end end|| loop loop if B emit C; if B emit C; pause pause end endend Void foo() { switch (st) { switch (st) { 0: if (IN=3) 0: if (IN=3) st = 5; st = 5; goto L5; goto L5; 1: if (RES) 1: if (RES) st = 3; st = 3; goto L8; goto L8; } L5: switch L5: switch} Esterel C Flow similar to Lin [DAC ‘98]

Copyright © 2001 Stephen A. Edwards All rights reserved Step 1: Build Concurrent CFG every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end RESET

Copyright © 2001 Stephen A. Edwards All rights reserved Add Threads every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end RESET Fork Join

Copyright © 2001 Stephen A. Edwards All rights reserved Split at Pauses every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end 2 1s RESET 2 1

Copyright © 2001 Stephen A. Edwards All rights reserved Add Code Between Pauses every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end s=2 D C B A 2 1s s=1 RESET

Copyright © 2001 Stephen A. Edwards All rights reserved Build Right Thread every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end s=2 C B D C B A 2 1s s=1 RESET

Copyright © 2001 Stephen A. Edwards All rights reserved Step 2: Schedule s=2 C B D C B A 2 1s s=1 RESET Add arcs for communication  Topological sort  Optimal scheduling: NP- Complete  “Bad” schedules OK

Copyright © 2001 Stephen A. Edwards All rights reserved Step 3: Sequentialize  Hardest part: Removing concurrency  Simulate the Concurrent CFG  Main Loop: For each node in scheduled order,  Insert context switch if from different thread  Copy node & connect predecessors

Copyright © 2001 Stephen A. Edwards All rights reserved Context Switching Code s=0 r 021 s=1s=2s=3 Save state of suspending thread Restore state of resuming thread

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Run First Node RESET

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Run First Part of Left Thread B A 2 1s RESET A 1s B 2

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Context switch: Save State t=0t=1 RESET A 1s B 2

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Rejoin t=0t=1 RESET A 1s B 2

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Run Right Thread t=0t=1 C B RESET A 1s B 2 BC

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Context Switch: Restore State t=0t=1 RESET A 1s B 2 BC t 01

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Resume Left Thread t=0t=1 DC s=2s=1 s=2 D C s=1 RESET A 1s B 2 BC t 01

Copyright © 2001 Stephen A. Edwards All rights reserved s=2 C B D C B A 2 1s s=1 RESET Step 3: Finished t=0t=1 DC s=2s=1 s=2 C B D C B A 2 1s s=1 RESET A 1s B 2 BC t 01

Copyright © 2001 Stephen A. Edwards All rights reserved Existing Esterel Compilers Simulation Speed Capacity switch (st) { case 0: st = 1; break; case 1: Automata V3 [Berry ‘87], Polis [DAC ‘95]

Copyright © 2001 Stephen A. Edwards All rights reserved Existing Esterel Compilers Simulation Speed Capacity A = B && C; D = A && E; Logic gates V4, V5 [Berry ‘92, ‘96] Automata V3 [Berry ‘87], Polis [DAC ‘95]

Copyright © 2001 Stephen A. Edwards All rights reserved Existing Esterel Compilers Simulation Speed Capacity A = B && C; D = A && E; Logic gates V4, V5 [Berry ‘92, ‘96] Automata V3 [Berry ‘87], Polis [DAC ‘95] CNET [CASES 2k]

Copyright © 2001 Stephen A. Edwards All rights reserved Existing Esterel Compilers Simulation Speed Capacity Logic gates V4, V5 [Berry ‘92, ‘96] New Compiler Automata V3 [Berry ‘87], Polis [DAC ‘95] CNET [CASES 2k]

Copyright © 2001 Stephen A. Edwards All rights reserved Speed of Generated Code Size (source lines) Average cycle time (  s)

Copyright © 2001 Stephen A. Edwards All rights reserved Size of Generated Code Size (source lines) Object code size (K)

Copyright © 2001 Stephen A. Edwards All rights reserved Part 2 Present and Future Work

Copyright © 2001 Stephen A. Edwards All rights reserved New Projects  New Esterel compiler  Languages for Device Drivers  Languages for Communication Protocols

Copyright © 2001 Stephen A. Edwards All rights reserved ESUIF  New, open Esterel compiler designed for research Source distributed freely  Based on SUIF2 system (suif.stanford.edu)  Modular construction  Standard compiler approach Front end builds AST AST dismantled into intermediate form Intermediate form translated into low-level code C code ultimately produced

Copyright © 2001 Stephen A. Edwards All rights reserved ESUIF Status  Front-end written, accepts large Esterel examples  Dismantlers partially complete: intermediate form defined  Linker (run statement expansion) to be implemented  Back-end to be implemented

Copyright © 2001 Stephen A. Edwards All rights reserved Esterel Compilation Plans  Apply discrete-event simulation techniques Similar to the CNET compiler  Apply Program Dependence Graph representation Concurrent representation used in optimizing compilers  Apply “localized partial interpretation” to expand parts of the system into finite-state machines  Techniques will point the way for other synchronous, concurrent languages

Copyright © 2001 Stephen A. Edwards All rights reserved Languages for Device Drivers  Device drivers are those pieces of software that you absolutely need that never seem to work  Tedious, difficult-to-write  Ever more important as systems incorporate customized hardware

Copyright © 2001 Stephen A. Edwards All rights reserved Best To Date  Thibault, Marlet, and Consel  IEEE Transactions Software Engineering, 1999  Developed the Graphics Adaptor Language for writing XFree86 video card drivers  Report GAL drivers are 1/9 th the size of their C counterparts  No performance penalty

Copyright © 2001 Stephen A. Edwards All rights reserved GAL S3 driver (fragment) chipsets S3_911, S3_924; What driver supports port svga index := 0x3d4; Write address, then data port misc := 0x3cc, 0x3c2; register ChipID := sva(0x30); Logical register serial begin Access sequence for register misc[3..2] <= (3,-, -, -, -) W; seq(0x12) (-, PLL1, -, -, -) R/W; end; identification begin Rules for identifying card 1: ChipID[7..4] => (0x8 => step 2, 0x 9 => S3_928); 2: ChipID[1..0] => (0x1 => S3_911, 0x2 => S3_924);

Copyright © 2001 Stephen A. Edwards All rights reserved Future Device Driver Work  Develop language for network card drivers under Linux  Study many existing implementations  Develop prototype language, compiler  Explore challenge of porting to other OSes  Apply lessons to other classes of drivers

Copyright © 2001 Stephen A. Edwards All rights reserved Languages for Communication Protocols  Many optimizations for implementing protocol code Fast-path optimization Collapsing layers  Tedious to implement manually  Tend to obfuscate code  Too high-level to be applied to, say, C code  Domain-specific language would allow these optimizations to be automated

Copyright © 2001 Stephen A. Edwards All rights reserved Summary  Esterel language  Esterel compiler based on control-flow graph  ESUIF: New Esterel compiler under development  Languages for Device Drivers  Languages for Communication Protocols