1 DESIGN OF 8-BIT ALU Vijigish Lella Harish Gogineni Bangar Raju Singaraju Advisor: Dr. David W. Parent 8 May 2006

2 Agenda Abstract Introduction Summary of Results Project (Experimental) Details Results Conclusions

3 Abstract The Aim of the project is to design a 8-bit ALU. The circuit is designed so as to meet the following specifications: –Frequency: 200 MHz. –Power : 100 mW. –Area : 576x840 µm 2 The design was done in AMI06 technology using Cadence tools.

4 Introduction Why this project? The ALU is a fundamental building block of any computing system. Challenging to design a 18 logic level design using CMOS Technology. Design consists of different kinds of logic… Brent-Kung Adder, DFF, AOI3333, Mux, Inv, Nand, Nor, Xor, etc.

5 Design Flow Selection of Adder Timing and Power Analysis Calculations for the Critical Path Gate level Design Functional Table NC Verilog Verification DRC & LVS for each bit Layout of Individual cells Schematic of Individual cells Final DRC & LVS Integration of bits

6 Project Summary The ALU performs 1 Arithmetic function and 9 Logical functions at 200MHz. Uses Brent Kung Adder to perform addition. Design uses maximum power of 100mW Maximum area is 576 x 840µm 2

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9 Schematic

ADD AxorB AB A+B AINV BINV Generate C1 C2 C3 C4 C5 C6 C7 C8 Propagate NAND M OR NOR XNOR

11 Longest Path Calculations Total Propagation delay for the longest path = 3.72ns INV AOI22 INV AOI22 XOR2 INV AOI21 INV NAND2 INV NAND2 INV NAND2 INV NAND2 INV AOI E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E  E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-04 GATEC intCgTphlNsnNspNMRWnWp FFscm

12 Simulation (Arithmetic operations)

13 Layout DFF INPUT OUTPUT

14 Verification

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17 Results The ALU performs all 10 functions at a 200MHz clock and a load of 20fF. Area of the layout is 576 x 840µm 2

18 Conclusions Designed a 8-Bit ALU that performs arithmetic and logical functions at 200MHz frequency driving up to 20fF. The Logic design can be modified to perform more functions.

19 Lessons Learned Cell based design Uniform cell height Floor planning Grid pattern for Vdd and gnd Debugging LVS errors using extracted view

20 Acknowledgements Thanks to Professor David W. Parent for his guidance. Thanks to Cadence Design Systems for the VLSI lab