Design Technology Center National Tsing Hua University A New Paradigm for Scan Chain Diagnosis Using Signal Processing Techniques Shi-Yu Huang ( 黃錫瑜 ) Jan. 6, 2006 National Tsing-Hua University, Taiwan Acknowledgements 曾昭文 楊振勳

2 Fault Models Scan Chain Faults Functional FaultsTiming Faults Setup-Time Violation Faults (Transition Faults) Stuck-at Bridging Slow-To-Rise Fault Slow-To-Fall Fault Hold-Time Violation Fault

3 A Stuck-At Fault In the Chain Effect: A killer of the scan-test sequence D Q input pins clock output pins D Q D Q Combinational Logic scan-input (SI) scan-output (SO) MUX scan-enable x s-a-0 ? All-0 syndrome

4 Definition: Snapshot Image input pins clock output pins Scan input (SI) Scan output (SO) Mission Logic 0 0 D Q MUX x s-a MUX Snapshot image: {(F 1, F 2, F 3, F 4 ) | (0, 1, 0, 1)} F1F1 F2F2 F3F3 F4F4 Def: A snapshot image is the combination of flip-flop values at certain time instance

5 Definition: Observed Image input pins clock output pins Scan input (SI) Scan output (SO) Mission Logic 0 0 D Q MUX x s-a MUX Snapshot image: {(F 1, F 2, F 3, F 4 ) | (0, 1, 0, 1)} Observed image: {(F 1, F 2, F 3, F 4 ) | (0, 0, 0, 1)} F1F1 F2F2 F3F3 F4F4 Def: An observed image is the scanned-out version of a snapshot image.

6 Test Application: Scan-Capture-Scan 1000 core logic x 1011 Step 1: Scan-in an ATPG pattern 0110 core logic x 0110 core logic x 0010 Step 2: Capture the response to FF’s Step 3: Scan-out and compare SI SO down-stream part Is distorted S-A-0 up-stream part will be distorted S-A-0

7 Test Application: Run-and-Scan Step 1: Apply a sequence of functional patterns from PI’s  Setting up a snapshot image at FF’s Step 2: Scan-out an observed image 0110 core logic x 0010 SO S-A-0 up-stream part will be distorted Less distorted image Test Sequence The fault location is embedded in the observed image

8 Prior Works & Our Advantages  Previous works  Hardware Assisted Extra logic on the scan chain [Edirisooriya 1995] [Nayaranan 1995] [Wu 1998]  Fault Simulation Based To find a faulty circuit matching the syndromes Tightening heuristic  upper & lower bounds [Kundu 1993] [Cheney 2000] [Stanley 2000] [Guo 2001][Y. Huang 2003, 2004, 2005]  Advantages of our approach  (1) Use signal processing techniques  (2) Fault model independent  (3) More capable of handling bridging faults

9 Outline  Introduction  Proposed Approach - Test Sequence Generation - Profile Analysis  Experimental Results  Conclusion

10 Signal Frequency At Flip-Flops st vector2nd vector 3rd vector 0 0 First flip-flop F1: {0, 0, 0, 0}  signal-1 frequency 0 (to be improved) Second flip-flop F2: {0, 1, 0, 1}  signal-1 frequency 0.5 (better) Mission logic Mission logic Mission logic 1st frame2nd frame3rd frame Reset State Observed Image F1 F2 A good set of test sequences  should make each FF as random as possible

11 Diagnostic Test Sequence Selection th 0 0 1st2nd rd4th th6th Selected clock cycles {1, 4, 5, 7}: 1st sequence 2nd sequence 3rd sequence 4th sequence 1 st sequence: {v 1 } 2 nd sequence: {v 1, v 2, v 3, v 4 } 3 rd sequence: {v 1, v 2, v 3, v 4, v 5 } 4 th sequence: {v 1, v 2, v 3, v 4, v 5, v 6, v 7 } reset

12 Interleaved Random-Shift Sequences The advantages of interleaved random-shift sequences:  The sequence is shorter in order to randomize FF values  The fault contamination is less Shift by one bit 0 0 2nd1st reset 0 1 2nd 1 0 Shift by one bit Observed Image Random Vector Random Vector Random Vector

13 Signal Profiling A profile is the distribution of certain statistics of the flip-flops. Fault-free model Faulty flip-flop Up-streamDown-stream core logic Test Sequences fault-free image Scan Shifting core logic perturbed image Failing chip x similar different Fault-free profile Comparing failing profile with the fault-free profile  Could reveal the fault location

14 Profile Analysis Fault-free images (say 100 of them) Failing images (say 100 of them) report a ranked list of fault locations Derive the fault-free profile Derive the failing profile Derive the difference profile Perform filtering on the difference profile Perform edge detection to derive ranking profile difference profile = fault-free profile ⊕ failing profile Collected from tester Details of filtering and edge detection are referred to the paper.

15 Example: Single Stuck-At Fault Example: FIR filter Scan chain: 160 flip-flops Fault injected: 80-th FF Fault-free Profile Faulty Profile Signal-1 Frequency (%) Scan Input  FF index  Scan Output Fault-Free Profile Failing Profile

16 Why Smoothing the Difference Profile?  There are lots of ripples on the raw profiling  We wish to capture the trend Difference profile Scan-InScan-Out Signal-1 Frequency

17 Running-Sum Filtering Notations: D[i]: The signal-1 frequency for i-th FF in Difference Profile SD[i]: The signal-1 frequency of i-th FF in Smoothed Difference Profile SD[i] = 0.2(D[i-4]+D[i-3]+ D[i-2]+ D[i-1]+ D[i])

18 Edge Detection

19 Example: Filtering & Edge Detection Signal-1 Frequency (%) Difference Profile Smooth ProfileRanking Profile Filtered Difference Profile Filtering & Edge Detection Scan Input  FF index  Scan Output

20 Example: Double Transition Faults FIR: 1 chain of 160 cells DFF80 DFF40 Fault-free Profile Faulty Profile Fault-Free Profile Failing Profile Signal-1 Frequency (%) Scan Input  FF index  Scan Output The difference is not as prominent here as that for stuck-at faults.  However, our profile analysis still works well.

21 Example: Double Transition Faults (cont’) Signal-1 Frequency (%) Ranking Profile Filtered Difference Profile Scan Input  FF index  Scan Output Difference Profile Scan Input  FF index  Scan Output

22 Outline  Introduction  Proposed Approach  Experimental Results  Conclusion

23 In-House Test Cases Design Name Size (# Gates) # Scan FF’s # of Images Used (1) GCD1.5k66500 (2) Montgomery Inverse 4.5k (3) Viterbi Decoder 9.5k (4) FIR Filter11k We assume one scan chain for a design Diagnostic test sequences are derived by interleaved random-shift operations

24 Result (1): Single Fault in the Chain Design 1st – hit indexSuccess Rate Stuck-AtBridgeTransitionStuck-AtBridgeTransition GCD %98%100% MON %92%96% FIR %98%100% VITERBI %95%94% Average %96%97.5% (Quality Metrics): (1) Success rate: The percentage of finding a fault in top-10 candidates (2) 1 st -hit index: The first candidate that turns out to be a real fault.

25 Result (2): Single Fault + Faulty Logic Design 1st – hit indexSuccess Rate Stuck-AtBridgeTransitionStuck-AtBridgeTransition GCD %98%97% MON %92%91% FIR %98%95% VITERBI %95%92% Average %96%93.75% (Quality Metrics): (1) Success rate: The percentage of finding a fault in top-10 candidates (2) 1 st -hit index: The first candidate that turns out to be a real fault.

26 Conclusion  Limitations of Existing Methods  (1) More or less bound to certain fault models  (2) Not suitable for bridging faults  (3) Not suitable for intermittent faults  Our contributions  Use signal processing techniques  Free of Fault Models  Good for stuck-at, transition, bridging, etc.  Works well when the core logic is also faulty