1 CS 140 Lecture 18 Sequential Modules: Serial Adders, Multipliers Professor CK Cheng CSE Dept. UC San Diego.

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Presentation transcript:

1 CS 140 Lecture 18 Sequential Modules: Serial Adders, Multipliers Professor CK Cheng CSE Dept. UC San Diego

2 Overview Introduction Serial Adder Multiplication Conclusion

3 Sequential Modules: Introduction Slice operation bitwise Perform process in a series of time Ad: Cheaper hardware, Fit for FPGA architecture, Pipelining for excellent throughput Dis: Longer latency

4 Serial Adder: Perform serial bit-addition a 0 b 0 a 3 b 3 c in c out s0s0 s3s3 Serial Adder abab sum sisi aiai bibi At time i, read a i and b i. Produce s i and c i+1 Internal state stores c i. Carry bit c 0 is set as c in

5 Serial Adder using D F-F D Q Q’ Clk sisi aiai bibi C1 D Feed a i and b i and generate s i at time i. Where is c i and c i+1 ?

6 Serial Adder using a D Flip-Flop idaiai bibi cici c i+1 sisi D=c i+1 Q=c i

7 D Q Q’ Clk sisi aiai bibi cici Serial Adder using a D Flip-Flop Logic Diagram

8 Serial Adder using an SR Flip-Flop Excitation Table idaiai bibi c i (Q) c i+1 SR SR generate c i+1 Q=c i

PS inputs State table Q(t+1) SR S aiai bibi cici R aiai bibi cici 0101 PS NS Q(t+1) Q(t) Excitation table Excitation Table of SR Flip-Flop

10 aiai SRSR Q Q’ sisi Clk cici bibi aiai bibi S = a i b i R = a i ’b i ’ Serial Adder using an SR Flip-Flop Logic Diagram

11 Multiplication using Serial Addition a 2 a 1 a 0 b 2 b 1 b 0 x a 2 b 0 a 1 b 0 a 0 b 0 a 2 b 1 a 1 b 1 a 0 b 1 + m0m0 m1m x X 5 = 15 For m=AxB, set m (0) =0 At time i, perform m (i+1) =m (i) +Ab i 2 i

12 Conclusion Exploration of silicon area and time domain design space Utilization of FPGA architecture Metrics of Cost, Speed, and Power