FUNDAMENTALS OF SINGLE CHIP PACKAGING Marko BUNDALO Derek LINDBERG

Chapter Objectives Single chip package (SCP) Functions of a SCPs Types of SCPs Fundamentals of SCP Materials, Processes, Properties Characteristics of SCPs

Introduction SCP – components (IC) onto system-level boards Plastic – low cost Ceramics – high thermal performance & reliability Recent trend – area array packages: ball grid array (BGA) chip scale package (CSP)

7.1 Single chip package (SCP) 7.2 Functions of a SCPs 7.3 Types of SCPs 7.4 Fundamentals of SCP 7.5 Materials, Processes, Properties 7.6 Characteristics of SCPs 7.7 Summary and Future Trends

7.1 Single Chip Package SCP supports a single microelectronic device Electrical, thermal, chemical performance adequately served Wafer Diced Packaged Burnt-in Tested Packaged IC = (few to million) of transistors Example of SCP – Intel’s ceramic pin grid array – generations of X86 family microprocessors

Active vs. Passive devices ACTIVE devices Memory or microprocessor Active – device capable of modifying and enabling the information in accordance with the logical instruction set. PASSIVE devices Resistors, capacitors, inductors Do not alter the transmitted signal Serve to optimize the performance and function Chapter 11

Examples of SCP More than one ACTIVE device multichip package (MCP) or multichip module (MCM) System designers - Combination of PASSIVE components, SCPs, MCM to meet application needs of the system. Examples of SCP for common applications:

7.2 Functions of a SCPs 7.1 Single chip package (SCP) 7.3 Types of SCPs 7.4 Fundamentals of SCP 7.5 Materials, Processes, Properties 7.6 Characteristics of SCPs 7.7 Summary and Future Trends

7.2 Functions of a SCPs Product life varies Primary function – enable the device/chip Perform its designed functions in a reliable manner Product life varies 1-2 years or less – cell phones and microprocessors for PCs 15-20 years – public exchange telecommunication switches Up to 40 years – military and aerospace applications EVERY single chip package MUST perform 6 functions: Signal transmission and power distribution TO and FROM the IC Signal transmission and power distribution BETWEEN the package device and other components. Enable device to be ATTACHED to the next level of packaging Allow for effective DISSIPATION OF HEAT generated by the package Provide adequate PROTECTION of the device Act as SPACE TRANSFORMER between the fine pitch grid and the PWB pitch grid Single chip package needs to deliver the best possible performance at the lowest possible cost.

7.3 Types of SCPs 7.1 Single chip package (SCP) 7.2 Functions of a SCPs 7.3 Types of SCPs 7.4 Fundamentals of SCP 7.5 Materials, Processes, Properties 7.6 Characteristics of SCPs 7.7 Summary and Future trends

7.3 Types of SCPs Single chip packages classified into three types: PTH (pin-through-hole) SMT (surface mount technology) SMT-Area Array

Microprocessor evolution during last three decades IBM (CISC – complex instruction set computing) Apple (RISC – reduced instruction set computing) Ceramic Pin-Grid-Arrays (PGAs) used SCP since 1982 Ease of pluggability and removal for IC repair Proven reliability Area array connections Compatible PWB availability Plastic (PGAs) replaced ceramic Recently, build-up or high-density Ball-Grid-Array (BGA) Lower cost Higher electrical performance

Table - Types of single chip packages, I/O, pitches and volumes In memory – plastic packages and lower pin count higher volumes Higher priced ceramics packages, high pin count lower volumes BGA emerges as dominant in future Joint Electronic Device Engineering Council – establishes the package geometry This body mandates standard dimensions for types of packages Companies provide set of technical specifications Material of construction, dimensional features, electrical, thermal and reliability performance

Logic and Memory Packages Total number of package pin outs to the PWB depends upon data being processed Total pin counts vary from few dozen to over a thousand Memory chips – few I/O pins Logic chips – higher number of gates/circuits – more pins Wide bandwidth networking switches for transmission over the internet – over 1000 I/O pins Package pins distributed between: Signal Power Common reference voltage or ground System performance ↑ - total pin count ↑ High performance - ↑ power and ground pins in order to reduce electrical noise during fast circuit switching.

7.4 Fundamentals of SCP 7.1 Single chip package (SCP) 7.2 Functions of a SCPs 7.3 Types of SCPs 7.4 Fundamentals of SCP 7.5 Materials, Processes, Properties 7.6 Characteristics of SCPs 7.7 Summary and Future trends

7.4 Fundamentals of SCP The need for I/O determined be Rent’s Rule Designers use it in estimating the number of required package pins or I/O terminals (N), given the total number of gates (M) K is constant – the average number of terminals required by one logic circuit p is constant – depends on system type Four main classes of application: 1. memory (static and dynamic RAMs) 2. microprocessors 3. gate arrays (FPGAs) 4. high-performance custom logic chips (“supercomputers”)

Relationship between chip I/Os and the number of chip circuits for various applications

I/O Pitch and Distribution I/O pitch defined Peripheral vs. Area (BGA) 20mm package at 0.2mm pitch – 10,000 I/Os

What package to use – board assembly yield The first pass manufacturing yield at IC assembly for various packages are: The most important reasons for these yields: Contribution of the pitch Self-alignment of solders to minimize shorts between two neighboring connections Coplanarity of leads parallel to the board Solder wetting Solder ball collapse

Materials Influence Performance Electrical Performance RC delay – influence the speed of signal propagation through the package V = C / square root of dielectric constant V is signal propagation C is speed of light

Thermal Performance Thermal dissipation capabilities dependent on the materials with which SCP are made. Intel’s microprocessor ICs – 4W in 1989 30W currently 100W in near future

Single Chip Packages Peripheral: DIP to PLCC to QFP to fine pitch QFP DIP, SOP, and QFP Area Array: Ceramic and plastic PGA to BGA to fine pitch BGA Flip Chip: Ceramic flip chip to organic flip chip

DIP: Dual In line Package Invented by Bryan Rogers in the early 1960s with 14 leads Adopted by Texas Instruments in 1962 Plastic or Ceramic version Earliest industry standard Low pin counts – 8 to 48 pin range Memory and logic microcontrollers Interconnect to the next level provided by copper Lead pitches of 1.75mm and 2.5mm Not preferred when space is a critical design constraint

SOP: Small Outline Package Well-suited for 24 to 48 pin memory packaging Cell phones, pagers, PCMCIA cards Similar to DIP by using copper leadframe for pins Leads have minimum standoff – making it easier to use in a surface mount assembly process to attach to the circuit board.

QFP: Quad Flat Pack Plastic QFP – established member of the family of peripherally-leaded packages Main difference – runs around all four sides Enables higher pin count – up to 304 pins The most common usage – 48 to 128 range Very popular choice for lower cost microprocessors and other ICs for portable systems Ceramic QFP preferred when resistance to high temperatures and humidity becomes an important design parameter.

Area Array Packages The first high volume PGA package in 1982 1993, Motorola started shipping BGA Since, packages have been “hot spot” SOP and QFP more expensive Last few years – With finer pitch and lower cost, Chip Scale Package (CSP) count as low as 36 or less. CSP twice as expensive as small outline packages. High I/O for BGA, small size for CSP Distinguish between CSP and BGA: A Ball-Grid-Array is an array package with a ball pitch of 0.8mm or greater. Includes very high leadcount packages (>500 I/O) A Chip-Scale-Package is an array package with a ball pitch of 0.8mm or less (0.5, 0.75, or 0.8) and area no more than 50% more than the IC.

BGA: Ball Grid Array Advantages: Overcomes many size and performance limitations of peripherally-leaded packages Greater number of I/Os at larger pitch preventing solder shorts. Basic types: Plastic (PBGA) Ceramic (CBGA) Tape (TBGA) Advantages: Size Performance Ease of assembly

CSP: Chip Scale Package Size advantage. Only 50% larger area than the silicon wafer and only 20% larger circumference. This makes it one of the most important package types.

Materials, Processes, and Properties Typical elements of an SCP: Base substrate for wiring Interconnects between chip and package Interconnect scheme between package and PCB Encapsulation to mechanically and chemically protect the chip and for thermal management Adhesive materials to attach chip to substrate (underfill) Materials chosen must be: Physically strong Corrosion resistant Withstand temperature and environmental conditions

Materials Common Package Materials: Plastic molding compounds (QFPs) Organic laminates such as FR-4, BT-epoxy (BGAs) Ceramics, both high (HTCC) and low temperature (LTCC) used in PGAs and BGAs Thin film flex and tape matreials By volume the majority of SCPs are laminates Manufacturability in large arrays makes them cheap Ability to use copper conductors can give better electrical performance High-frequency and high pin count use ceramics Most common is alumina or HTCC Superior strength, moisture, and temperature tolerance High processing temperature requires molybdenum or tungsten conductors

Encapsulants, Lids, and Adhesives Package type and application specific: Copper lids or slugs in contact with the silicon can provide an improved thermal interface Low cost molding compounds or “globtops” can be used to seal and protect devices Variety of adhesives are used to attach the device to the package: Silver filled epoxy Gold/gold-silicon compounds

Electrical Characteristics Basic parameters of a package are: Line resistance Loading capacitance Inductance Models used to evaluate SCPs must account for all elements of a package A good package exhibits minimum switching noise at the frequencies of operation

Packaging Efficiency Ratio of IC area to Package area Very critical in portable electronics

Reliability A major issue with Medical devices High up-time devices Automotive and airborne components Full testing suite might take 4+ months to run Accelerated testing of expected loads: Thermal shock Shipping shock Vibration Humidity Chemical exposure

Cost Price premium for clock speed Relative cost of package to IC will determine what format is used Higher cost BGAs and CSPs can be justified for decreased size

Future Trends Trends driven by size, cost, reliability and increasing electrical performance.