1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 8 MAD MAC nd March, 2006 Functional Block and Simulations W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small blocks Large block layouts, extractions, LVS, simulations (in progress) Spring Break  To be done  Full chip layout and simulation

3 RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator Input Output 16 Reg Y Block Diagram

4 Design Decisions Pipelining Stages: Add another stage in multiplier since adder is very fast. –Projected speed is at least 400 MHz –Exceeds the design goal of 300MHz

5 Pipelining Stages Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Pipeline Reg Overflow checker Pipeline Reg

6 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Pipeline stage 5 Multiplier lower 7 outputs Multiplier mid 4 outputs Multiplier top 11 outputs AdderNormalize Exponent calculator Holds exponent calculator? AlignZero Counter Round Holds exponent calculator bits Overflow Checker

7 New Floorplan

8 Design Decisions Pipelining Stages: Add another stage in multiplier since adder is very fast. –Projected speed is at least 400 MHz –Exceeds the design goal of 300MHz Optimized adder design which implements carry look ahead architecture –Propagation delay of around 800ps (1250MHz) –Bit slicing the adder in the layout

9 Adder Schematic

10 Adder Schematic Simulation

11 Adder Bit Slice Layout

12 Transisto r Count Area in um 2 Prop. Delay Power in mW (350MHz) Multiplier n8.5 Exponents p1.608 Align p0.393 Adder n5.236 Leading p0.857 Normalize p2.291 Round p0.631 OvfCheck p0.13 Registers p- Total

13 Optimized Round Schematic

14 Normalize Layout

15 Align Layout

16 Align Simulation

17 Exponents progress…

18 Questions??