Joshua GarrettUniversity of California, Berkeley SpecCharts: A VHDL Front-End for Embedded Systems

Joshua GarrettUniversity of California, Berkeley Motivation VHDL Widely used for hardware description Supported with powerful synthesis and verification tools Embedded Systems Functional specification is preferred Specifying embedded systems in VHDL tedious, time-consuming, and error-prone SpecCharts: a VHDL front-end for embedded systems

Joshua GarrettUniversity of California, Berkeley Specifying Embedded Systems Derive implementation from an informal specification “English” to gate-level netlist/C code Benefits of a functional specification Functional errors can be identified early in the process Facilitates integration with concurrently-designed systems Automated estimation and synthesis tools Reduce design time Evaluate alternative implementations Can redesign for another application without reverse engr. Isn’t VHDL code a functional specification…?

Joshua GarrettUniversity of California, Berkeley Embedded Systems …yes, but not a good one. Characteristics common to embedded systems: 1. Sequential and concurrent behavior decomposition 2. State transitions 3. Exceptions 4. Sequential Algorithms 5. Behavior Completion Support: A description language supports a characteristic if there is a simple, direct mapping of the characteristic to a language construct VHDL fully supports sequential decomposition and sequential algorithms, but not the rest

Joshua GarrettUniversity of California, Berkeley VHDL Limitations for Embedded Systems Sequential and Concurrent Behavior Decomposition VHDL supports concurrent decomposition of top-level functionality using processes, but not concurrent decomposition of a process Q and R and forked sub-behaviors of process Main Q, R are not concurrently executed with P, S

Joshua GarrettUniversity of California, Berkeley VHDL Limitations for Embedded Systems State Transitions Loop and case statements Difficult to discern state transitions without mentally executing VHDL code

Joshua GarrettUniversity of California, Berkeley VHDL Limitations for Embedded Systems Exceptions VHDL does not possess a construct to immediately deactivate a process or procedure upon the occurrence of an event Coerce exception handling by polling for the exception throughout the behavior’s sequential statements

Joshua GarrettUniversity of California, Berkeley VHDL Limitations for Embedded Systems Sequential Algorithms Fully supported Behavior Completion Procedure completion supported (return statement) Process completion is not Add a signal which is asserted at the end of a process Monitored by other processes Could we do better with another language?

Joshua GarrettUniversity of California, Berkeley Functional Specification Language Comparison Verilog, Esterel: support fork/join, behavior disable, but not state transitions Communicating Sequential Processes (CSP): fork/join, but not state transitions or exceptions Statecharts, Argos: permits hierarchical/concurrent FSM, but not sequential algorithms Specification and Description Language (SDL): state transitions inside processes and behavior completion, but no exceptions or sequential algorithms

Joshua GarrettUniversity of California, Berkeley SpecCharts We can coerce embedded system behavior out of VHDL, but: May be extremely tedious, time-consuming, and error prone Resulting description may be difficult to comprehend SpecCharts Introduce Programming State Machines (PSM) Hierarchical/concurrent FSM with programming language paradigm Program state is a three-tuple

Joshua GarrettUniversity of California, Berkeley SpecCharts Compact description in SpecCharts

Joshua GarrettUniversity of California, Berkeley Translation into VHDL Isn’t this still just VHDL? VHDL simulators are widely used, fast, and reliable VHDL is required documentation for many projects Synthesis and verification tools take VHDL as input VHDL translation algorithm is focused on readability, simulation efficiency, and synthesizability SpecCharts behavior -> VHDL process Hierarchy is maintained PSM program states each represented by its own process Synthesis of SpecCharts Tools assume 1 controller, 1 datapath per process Sequential behaviors should be flattened in translation

Joshua GarrettUniversity of California, Berkeley Measuring the Utility of SpecCharts Human Test Subjects Specification Capture Specification Comprehension Specification Quantification Design Quality Translation E.g. Six subjects (three using VHDL, three using SpecCharts) given documentation for an existing aircraft traffic-alert and collision-avoidance system. Subjects took 2.5x time more time to specify the system in VHDL, 2/3 VHDL specifications contained a major control error, and only 1/2 was able to correct that error in the allotted time.

Joshua GarrettUniversity of California, Berkeley Measuring the Utility of SpecCharts Specification Comprehension Modelers given VHDL specification took 3x longer to understand the general behavior, e.g. “What happens when the Enable signal goes low”, average 2/14 wrong answers. Specification Quantification SpecCharts specification uses ~4x less words than even hierarchical VHDL, and 1/2 as many states as Statecharts Design Quality Design derived from English/SpecCharts specification show little difference in final transistor count Translation Simulation of translated SpecCharts code is slower than handwritten VHDL, but by less than an order of magnitude (550s as compared to 220 and 250s)

Joshua GarrettUniversity of California, Berkeley Conclusion Existing languages don’t support direct specification of common embedded system characteristics New conceptual computation model, PSM Language based on that model, SpecCharts Built on a popular standard language, VHDL Fits well with current methodologies Can lead to fewer functional errors and easier integration of system models Fewer design iterations, fast time-to-market, improved product support