Using SuperVISE for Software Design Validation III Peter Henderson and Bob Walters

Ideas from SuperVISE n Ideas in SuperVISE would be helpful in a software environment – Models to confirm requirements – Models to evaluate designs – Multilevel modelling – Refining models into implementations n Still useful without tool support

A tool for system development

"Super-SuperVISE" n A new higher level modelling tool n Would use a new language n Hardware/software neutral n Integrated with other tools for development

"SV-Soft" n Similar in concept to SuperVISE n Aimed at software projects n Needs to appeal to software developers – Familiar looking language – Easy and quick to use n New language

Considerations for a language n Follow pattern of software languages n Communications “models” n Types of pieces in models n How to assemble complete model

Outline of a candidate language for "SV-Soft" n Descriptions of the components n Description of interfaces n Building the system n SV-Soft and VHDL+

Simple Example

Descriptions of the components Component A level 1 Uses Interface I Port A1: P1.C of I Begin /* Description of behaviour of an A */ … A1.c1( … ) … End

Description of interfaces Interface I Ports P1, P2 Exports C, D, E Class C on P1 Method c1( … )Event c2( … )…End Class C on P2 Event c1( … )Method c2( … )…End Class D on P1 /* Implementation details of C, D … */ End Interface

Building the system System S InstA : A InstB : B InstI : I Begin Map (InstA.A1, InstI.P1) Map (InstB.B1, InstI.P2) End

SV-Soft and VHDL+

Future Work n “SV-Soft” Language n Development of tool support for “SV-Soft”

Summary n Ideas and concepts from SuperVISE appropriate to software n How SuperVISE might fit n “SuperSuperVISE” n New language for software n Future plans