TigerSHARC processor General Overview

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 2 Concepts tackled Introduction to capabilities of TigerSHARC ADSP-TS201 processor – Warning – you have TS201S instruction manual and TS101S hardware manual. At the moment the TS201S hardware manual is only available on the web

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 3 Processor Architecture bit data busses 2 Integer ALU 2 Computational Blocks – ALU (Float and integer) – SHIFTER – MULTIPLIER – COMMUNICATIONS CLU

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 4 Integer ALU Except for NO multiplier capability, essentially “processor” unit with capabilities of a 68K or MIPS processor Intended more as DAG Data address generator, but can do integer math.

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 5 X and Y Register File X – 32 locations Y – 32 locations Holds “bit patterns” Those bit patterns can be “floating point number” bit patterns OR “integer number” bit patterns BUT NOT BOTH AT THE SAME TIME 10% of marks lost in final and midterm will be associated with not understanding this issue. (30% of time wasted in labs too)

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 6 X and Y ALU Can handle floating point and integer operations by taking “bit patterns” from register file and do operations on them Very flexible 10% of marks lost in final and midterm will be associated with not understanding this functionality. (30% of time wasted in labs too)

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 7 SHIFTER Can handle integer operations by taking “bit patterns” from register file and do operations on them Very flexible 10% of marks lost in final and midterm will be associated with not understanding this functionality.

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 8 MULTIPLIER Multiplies integer and floating point “bit patterns” from register file Very flexible 10% of marks lost in final and midterm will be associated with not understanding this functionality. (15% of time wasted in labs too)

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 9 CLU VERY, VERY FANCY COMPLEX ARITHMETIC (2, 8 and 16 bits) TRELLIS, VERTIBBI etc Capability, excellent individual projects, also Q9 on final exam (D-I-Yourself)

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 10 J and K DATA BUSES VERY FANCY 32-bit accesses 64-bit accesses 128-bit accesses 256-bit loads possible (128 to 4 X registers and 128 to 4 Y registers) Some special issues when loading QUAD values (4 at same time) that are offset handled with DAB (data address buffer?)

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 11 I-BUS DATA BUS VERY FANCY VLIW – very long and variable length instruction word 32-bit accesses done with IAB 64-bit accesses done with IAB 96-bit accesses done with IAB 128-bit accesses done with IAB BTB (Branch target buffer) assists with many pipeline issues 10% of marks lost in final and midterm will be associated with not understanding this functionality.

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 12 Pipeline issues -- Normal instruction

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 13 Terminology – C++ compiler often inserts comments about “bubbles” Instr 2 needs result from instr1 But Instr1 result not available till end of pipeline so Instr 2 stalls

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 14 Not entirely clear of explanation seems 1 cycle out by my model STALL BUBBLE Once the STALL is broken, then a BUBBLE (virtual NOP?) is inserted into the instruction stream

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 15 Many types of coding used in this course Compiler “debug” mode – inefficient code Compiler “release” mode – more efficient code (inter-procedural optimization, general parallel instructions). – Use the.s output as a starting point for optimizing assembly code and for learning about instructions and optimizing techniques Custom Assembler “SISD” “debug mode” – not highly optimized, but no general inefficiencies. Lab1 and Lab. 2. Generally quizable. Custom Assembler “SISD” and “SIMD” “release modes” – coded in a way that we “avoid” probable stalls, rather than completely understanding them. Lab. 2 and Lab. 3. Somewhat quizable. Custom Assembler “SISD”, “SIMD” and “MIMD” “highly optimized mode”. Understanding the concepts, very difficult to put actual questions into a quiz (too time consuming). Probably demonstrable in final lab. Lab 4 – individual assignments. Need to know “what to worry about” Dual processor mode – all of the above. Probably demonstrable in final lab. Lab 4 – individual assignments. Need to know “what to worry about”

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 16 Predicted jump – BTB hit BIG DELAYS NO DELAYS

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 17 Predicted jump – BTB miss BIG DELAYS

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 18 Non predicted branches XY – big loss

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 19 Non predicted branches JK – less loss

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 20 Pipeline issues – Predicted – not taken

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 21 Pipeline issues -- many Predicted Branch not taken R1 = R2 + R3;; R0 = [J1 += J5];; R4 = R5 + R1;; Conflict on J-bus Data dependencies Sort of acts like Sort of acts like R1 = R2 + R3;; R0 = [J1];; stall J1 = J1 + J5;; R4 =R4 + R1;;

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 22 Pipeline issues -- many R1 = R2 + R3;; R0 = [J1 += J5];; R4 = R5 + R1;; Conflict on J-bus Data dependencies Sort of acts like Sort of acts like R1 = R2 + R3;; R0 = [J1];; stall J1 = J1 + J5;; R4 =R4 + R1;;

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 23 Pipeline issues -- many Predicted Branch not taken R1 = R2 + R3;; R0 = [J1 += J5];; R4 = R5 + R1;; Conflict on J-bus Data dependencies Sort of acts like Sort of acts like R1 = R2 + R3;; R0 = [J1];; stall J1 = J1 + J5;; R4 =R4 + R1;;

6/28/2015 TigerSHARC processor, M. Smith, ECE, University of Calgary, Canada 24 Concepts tackled Introduction to capabilities of TigerSHARC ADSP-TS201 processor – Warning – you have TS201S instruction manual and TS101S hardware manual. At the moment the TS201S hardware manual is only available on the web