Fibre Channel Video Controller Project Description Kapshitz Tsachy Grinkrug Michael

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion2 Introduction to Fibre Channel Computer communications protocol, designed to meet many different requirements: –Allow many existing channel and networking protocols run over same physical interface –High bandwidth (100 MB/s and even more) –Different topologies and long distance support –Error correction

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion3 Point to Point Topology Full Duplex point to point connection between 2 hosts Maximum bandwidth Simple link initialization

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion4 FC Frame Format SOF Frame Header 24 Bytes Data Field ( Bytes) Opt. HeadersPayload CRCEOF Fill Word(s) Fill Word(s) The frame is delimitated by SOF and EOF By relevant fields in Frame Header further processing is handled. CRC has to be checked for integrity

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion5 FC Frame Header In this header Destination_ID field and Type need to be checked If it matches host’s pre- configured Destination_ID and Type –the frame will be checked further –otherwise it will be ignored

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion6 The FC-AV Container System

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion7 The Goal of the Project Design a FC controller that will: –support the above Point to Point topology on receive side only –recognize FC Video frames directed to the host it resides in and capture them from the link –parse frame headers and according to the information found in them dump the video data into memory –process that with minimal latency

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion8 Input Interface of the Controller The Controller will function on FC-2 layer FC-0 and FC-1 layers will be handled by HDMP Receiver (HP®) or one of its kind Error Correction 8B/10B processing will not be processed by the controller FC Link Receiver FC Controller

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion9 Input Interface of the Controller FC Controller COM_DET RBC[1]RBC[0] RX[0:19 ] EN_ CDET PPSEL FC Interface Unit HDMP-1514 by HP®

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion10 Working Frequencies As long as the clock output from HDMP-1514 FC Receiver is the same for both 531 Mb/s and for 1062 Mb/s, we assume that side of the interface will function on ~53 MHz frequency (getting 1 or 2 bytes per clock according to the link speed).

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion11 Output Interface of the Controller Memory (SRAM) or, potentially, an LCD display The Video data that will be “grabbed” from the frames will be dumped to memory in its pixel order, respectively FC Controller Memory / LCD

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion12 Testing VHDL Test Bench (Input/Output file) Building some text generator, getting a video object in a file, and producing an appropriate container fragmented into frames. The output file will be compared with the original object-file.

6 April 2000T. Kapshitz & M. Grinkrug, Digital Systems Lab, Technion13 Assumptions No 8B/10B decoder will be implemented CRC integrity checking but no calculation Container in simplified mode Dest. ID and other configuration info will be statically defined. FC-0 and FC-1 layers will be handled by HDMP-1514 Receiver (HP®)