DARPA Reversible Logic Circuit Synthesis Vivek V. Shende, Aditya K. Prasad, Igor L. Markov and John P. Hayes University of Michigan

Outline Motivation Motivation Real-world Applications Real-world Applications Theoretical Advantages Theoretical Advantages Links to Quantum Computation Links to Quantum Computation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

Real-world Applications Many inherently reversible applications Many inherently reversible applications Info. is re-coded, but none is lost or added Info. is re-coded, but none is lost or added Digital signal processing Digital signal processing Cryptography Cryptography Communications Communications Computer graphics Computer graphics Network congestion modeling Network congestion modeling

Theoretical Advantages Information conservation laws in physics Information conservation laws in physics Thermodynamics ties irreversibility to dissipated heat: every lost bit causes an energy loss Thermodynamics ties irreversibility to dissipated heat: every lost bit causes an energy loss C. Bennett, 1973, IBM J. of R & D C. Bennett, 1973, IBM J. of R & D Energy-lossless circuits (Time  ∞ ) Energy-lossless circuits (Time  ∞ ) must be information-lossless must be information-lossless have been built: S. Younis and T. Knight, 1994, Workshop on Low Power Design have been built: S. Younis and T. Knight, 1994, Workshop on Low Power Design

Links to Quantum Computation Quantum operations are all reversible Quantum operations are all reversible M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge Univ. Press 2000 M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge Univ. Press 2000 Every (classical) reversible circuit may be implemented in quantum technology, with overhead Every (classical) reversible circuit may be implemented in quantum technology, with overhead “Pseudo-classical” subroutines of quantum algos “Pseudo-classical” subroutines of quantum algos Can be implemented in classical reversible logic circuits Can be implemented in classical reversible logic circuits S. Betteli, L. Serafini, and T. Calarco, 2001, S. Betteli, L. Serafini, and T. Calarco, 2001,

Outline Motivation Motivation Background Background Reversibility Reversibility Permutations Permutations Known Facts Known Facts Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

Reversibility in Logic Gates Definition: reversible logic gate Definition: reversible logic gate #input wires = #output wires #input wires = #output wires Permutes the set of input values Permutes the set of input values Examples Examples Inverter Inverter 2-input, 2-output SWAP (S) gate 2-input, 2-output SWAP (S) gate k-CNOT gate k-CNOT gate (k+1)-inputs and (k+1)-outputs (k+1)-inputs and (k+1)-outputs Values on the first k wires are unchanged Values on the first k wires are unchanged The last value is flipped if the first k were all 1 The last value is flipped if the first k were all 1

Reversibility in Logic Circuits Definition: A combinational logic circuit is reversible iff Definition: A combinational logic circuit is reversible iff It contains only reversible gates It contains only reversible gates It has no fan-out It has no fan-out It is acyclic (as a directed multi-graph) It is acyclic (as a directed multi-graph) Theorem: A reversible circuit must Theorem: A reversible circuit must Have as many input wires as output wires Have as many input wires as output wires Permute the set of input values Permute the set of input values

A Reversible Circuit and Truth Table xyzx’y’z’ Equivalent to a single CNOT gate

Circuit Equivalences Circuit equivalences: useful in synthesis More will be shown later

Reversible Circuits & Permutations A reversible gate (or circuit) with n inputs and n outputs has A reversible gate (or circuit) with n inputs and n outputs has 2 n possible input values 2 n possible input values 2 n possible output values 2 n possible output values The function it computes on this set must, by definition, be a permutation The function it computes on this set must, by definition, be a permutation The set of such permutations is called S 2 n The set of such permutations is called S 2 n

Basic Facts About Permutations Permutations are multiplied by first applying one, then the other Permutations are multiplied by first applying one, then the other example: (1,2)◦(2,3) = (1,3,2) example: (1,2)◦(2,3) = (1,3,2) A transposition A transposition permutes exactly two elements permutes exactly two elements does not change any others does not change any others Every permutation can be written as a product of transpositions Every permutation can be written as a product of transpositions

Even Permutations Consider all possible decompositions of a permutation into transpositions Consider all possible decompositions of a permutation into transpositions Theorem: The parity of the number of transpositions is constant Theorem: The parity of the number of transpositions is constant Definition: Even permutations are those for which the number of transpositions is even Definition: Even permutations are those for which the number of transpositions is even

Known Facts Fact 1: Consider a reversible circuit Fact 1: Consider a reversible circuit n+1 inputs and n+1 outputs n+1 inputs and n+1 outputs Built from gates which have at most n inputs and n outputs Built from gates which have at most n inputs and n outputs Must compute an even permutation Must compute an even permutation Fact 2: A universal gate library Fact 2: A universal gate library CNOT, NOT, and TOFFOLI (“CNT”) CNOT, NOT, and TOFFOLI (“CNT”) Temporary storage may be required Temporary storage may be required

Temporary Storage

Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Zero-storage Circuits Zero-storage Circuits Reversible De Morgan’s Laws Reversible De Morgan’s Laws Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

Minimizing Temporary Storage Consider CNT circuits Consider CNT circuits Theorem: even permutations computable by circuits without temporary storage Theorem: even permutations computable by circuits without temporary storage Theorem: odd permutations computable with one line of temporary storage Theorem: odd permutations computable with one line of temporary storage Same holds for NT- and CNTS-circuits Same holds for NT- and CNTS-circuits The proof is constructive and may be used as a synthesis heuristic The proof is constructive and may be used as a synthesis heuristic

C- and N-circuits N-circuits need at most one gate per wire N-circuits need at most one gate per wire Can cancel inverters Can cancel inverters C-circuits on k wires act as k × k matrices C-circuits on k wires act as k × k matrices By reversibility, the matrix must be invertible By reversibility, the matrix must be invertible A C(x,y) gate is a row-addition matrix which adds the x-th row to the y-th A C(x,y) gate is a row-addition matrix which adds the x-th row to the y-th Can get all invertible matrices Can get all invertible matrices

T-circuits T-circuits fix 0, 2 i T-circuits fix 0, 2 i These have only one 1 in their binary expansion These have only one 1 in their binary expansion T-circuits on 4+ wires compute even perms. T-circuits on 4+ wires compute even perms. In fact, any circuit in which no gate involves all the wires computes an even permutation In fact, any circuit in which no gate involves all the wires computes an even permutation T. Toffoli, "Reversible Computing", Tech. Memo MIT/LCS/TM-151, MIT Lab for Comp. Sci, T. Toffoli, "Reversible Computing", Tech. Memo MIT/LCS/TM-151, MIT Lab for Comp. Sci, Any permutation satisfying the above constraints can be computed in a T-circuit Any permutation satisfying the above constraints can be computed in a T-circuit

T-circuits Assume #wires > 3 Assume #wires > 3 Decompose an even permutation into a product of disjoint transpositions Decompose an even permutation into a product of disjoint transpositions (a,b)(c,d) is okay, (a,b)(b,c) is not (a,b)(c,d) is okay, (a,b)(b,c) is not But (a,b)(b,c) = [(a,b)(d,e)] [(d,e)(b,c)] But (a,b)(b,c) = [(a,b)(d,e)] [(d,e)(b,c)] Explicitly construct a circuit to compute an arbitrary pair of disjoint transpositions Explicitly construct a circuit to compute an arbitrary pair of disjoint transpositions

Computing Disjoint Trans. Pairs Use an (n-2) generalized Toffoli gate on n wires Use an (n-2) generalized Toffoli gate on n wires Can compute z = (2 n -1, 2 n -2)(2 n -3, 2 n -4) Can compute z = (2 n -1, 2 n -2)(2 n -3, 2 n -4) Can be simulated by T gates (no temporary storage) Can be simulated by T gates (no temporary storage) A. Barenco et al.: ``Elementary Gates For Quantum Computation'', Physi. Review A (52), , 1995 A. Barenco et al.: ``Elementary Gates For Quantum Computation'', Physi. Review A (52), , 1995 Can compute a permutation p sending: Can compute a permutation p sending: a → 2 n -1, b → 2 n -2, c → 2 n -3, d → 2 n -4 a → 2 n -1, b → 2 n -2, c → 2 n -3, d → 2 n -4 Use these constructions to compute a given pair of disjoint transpositions Use these constructions to compute a given pair of disjoint transpositions p -1 zp = (a,b)(c,d) p -1 zp = (a,b)(c,d)

CT|N-circuits A CT|N-circuit is a CNT-circuit with all the N gates at the right end A CT|N-circuit is a CNT-circuit with all the N gates at the right end To convert a CNT-circuit into CT|N form To convert a CNT-circuit into CT|N form Write down rules for interchanging N gates with C and T gates Write down rules for interchanging N gates with C and T gates Push all the N gates to the end Push all the N gates to the end Like pushing inverters to the front of (irreversible) AND/OR/NOT-circuits Like pushing inverters to the front of (irreversible) AND/OR/NOT-circuits

Reversible De Morgan’s Laws

T|C-circuits Similar rules exist for interchanging TOFFOLI and CNOT gates Similar rules exist for interchanging TOFFOLI and CNOT gates

Reversible De Morgan’s Laws (2)

T|C-circuits However, it is not always possible to push all C gates to the inputs However, it is not always possible to push all C gates to the inputs A T|C-circuit’s permutation must fix 0, and map the elements 2 i to linearly independent vectors A T|C-circuit’s permutation must fix 0, and map the elements 2 i to linearly independent vectors Recall: T-circuits fix 0, 2 i, and C-circuits compute invertible linear transformations Recall: T-circuits fix 0, 2 i, and C-circuits compute invertible linear transformations A permutation can be computed by a T|C-circuit if it satisfies the above requirements A permutation can be computed by a T|C-circuit if it satisfies the above requirements The permutation (1,2)(3,4) does not The permutation (1,2)(3,4) does not We will see that it can be computed by a CT-circuit We will see that it can be computed by a CT-circuit

T|C|T-circuits Given any even permutation fixing zero Given any even permutation fixing zero Can multiply it by an even permutation fixing 0, 2 i so that the product fixes 0, and takes inputs 2 i to linearly independent outputs Can multiply it by an even permutation fixing 0, 2 i so that the product fixes 0, and takes inputs 2 i to linearly independent outputs A T-circuit can simulate the former A T-circuit can simulate the former A T|C circuit can simulate the latter A T|C circuit can simulate the latter So, any zero-fixing even permutation can be computed by a T|C|T-circuit So, any zero-fixing even permutation can be computed by a T|C|T-circuit

T|C|T|N-circuits Let p be an even permutation Let p be an even permutation There is an N-circuit taking 0 to p(0) There is an N-circuit taking 0 to p(0) Unique up to canceling redundant gates Unique up to canceling redundant gates Say this N-circuit computes the permutation n Say this N-circuit computes the permutation n The permutation pn -1 fixes 0, and can be computed by a T|C|T-circuit P’ The permutation pn -1 fixes 0, and can be computed by a T|C|T-circuit P’ Then the circuit P’N computes p Then the circuit P’N computes p Theorem: any even permutation can be computed by a T|C|T|N-circuit Theorem: any even permutation can be computed by a T|C|T|N-circuit

Comments on Circuit Length For “long” CNT-circuits, this algorithm produces circuits which are suboptimal by at worst a logarithmic factor (in the number of wires) For “long” CNT-circuits, this algorithm produces circuits which are suboptimal by at worst a logarithmic factor (in the number of wires) Converting a CNT-circuit to a CT|N-circuit increases circuit size by about a factor of 3 Converting a CNT-circuit to a CT|N-circuit increases circuit size by about a factor of 3 We do not know any good algorithm to convert CNT-circuits to T|C|T|N-circuits, or even if this conversion may be done with polynomial length increase We do not know any good algorithm to convert CNT-circuits to T|C|T|N-circuits, or even if this conversion may be done with polynomial length increase

Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits Optimality Optimality DFID Search Algorithm DFID Search Algorithm Circuit Libraries Circuit Libraries An Application to Quantum Computing An Application to Quantum Computing

Optimality The cost of a circuit is its gate count The cost of a circuit is its gate count Other cost functions can be considered Other cost functions can be considered Definition: optimal reversible circuit Definition: optimal reversible circuit no circuit with fewer gates computes the same permutation no circuit with fewer gates computes the same permutation Theorem: a sub-circuit of an optimal circuit is optimal Theorem: a sub-circuit of an optimal circuit is optimal Proof: otherwise, can improve the sub-circuit Proof: otherwise, can improve the sub-circuit

The Search Procedure Depth First Iterative Deepening Search Depth First Iterative Deepening Search Checks all possible circuits of cost 1, then all possible circuits of cost 2, etc… Checks all possible circuits of cost 1, then all possible circuits of cost 2, etc… Avoids the memory blowup of BFS Avoids the memory blowup of BFS Still finds optimal solutions (unlike DFS) Still finds optimal solutions (unlike DFS) Checking circuits of cost less than n Checking circuits of cost less than n Is much faster than processing cost-n circuits Is much faster than processing cost-n circuits

Dynamic Prog + Circuit Libraries DFID search requires a subroutine to check all circuits of cost n, for arbitrary n DFID search requires a subroutine to check all circuits of cost n, for arbitrary n Called iteratively for 1…n Called iteratively for 1…n Only need to check locally optimal circuits Only need to check locally optimal circuits Build optimal circuit library bottom up by DP Build optimal circuit library bottom up by DP Index optimal circuits by computed permutation Index optimal circuits by computed permutation In practice use hash_map datastruct from STL In practice use hash_map datastruct from STL

Synthesis Algorithm

Empirical Circuit Synthesis Consider all reversible functions on 3 wires (8! = 40,320 functions) Consider all reversible functions on 3 wires (8! = 40,320 functions) For each gate library from N, C, T, NC, CT, NT, CNT, CNTS For each gate library from N, C, T, NC, CT, NT, CNT, CNTS Is it universal? Is it universal? How many functions can it synthesize? How many functions can it synthesize? How long does it take to synthesize circuits? How long does it take to synthesize circuits? What are largest optimal circuits? What are largest optimal circuits?

Optimal Circuit Sizes SizeNCTNCCTNTCNTCNTS Total Time, s

Largest Optimal Circuits

Why Circuit Libraries? Large speedup relative to just branching Large speedup relative to just branching Can be calculated from previous table Can be calculated from previous table Calculated values are very large Calculated values are very large In practice, the table cannot be generated in several hours without circuit libraries In practice, the table cannot be generated in several hours without circuit libraries With libraries, the table takes less than 10 min With libraries, the table takes less than 10 min

Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing Grover’s Search Grover’s Search Pseudo-classical Synthesis Pseudo-classical Synthesis

Quantum Circuits Necessarily reversible Necessarily reversible Information stored on qubits Information stored on qubits Superposition allows linear combinations of 0 and 1 to be stored Superposition allows linear combinations of 0 and 1 to be stored All reversible gates still allowed All reversible gates still allowed Many other gates used as well Many other gates used as well

Grover’s Search A quantum algorithm for associative search (input is not sorted) A quantum algorithm for associative search (input is not sorted) Search criterion: a classical one-output function f Search criterion: a classical one-output function f L. K. Grover, “A Framework For Fast Quantum Mechanical Algorithms”, STOC 1998 L. K. Grover, “A Framework For Fast Quantum Mechanical Algorithms”, STOC 1998 M. Nielsen and I. Chuang, 2000 M. Nielsen and I. Chuang, 2000 Runs in time O(√N) Runs in time O(√N) any classical algorithm provably requires  (N ) time any classical algorithm provably requires  (N ) time Requires a subroutine (oracle) that Requires a subroutine (oracle) that changes the phase (sign) of all basis states (bit-strings) that match the search criterion f changes the phase (sign) of all basis states (bit-strings) that match the search criterion f

Grover Oracle Circuits To change the sign of a bit-string To change the sign of a bit-string Initialize a qubit to |0> - |1> Initialize a qubit to |0> - |1> Compute the classical one-output function f Compute the classical one-output function f XOR the qubit with f XOR the qubit with f Whenever f=1, the sign (phase) will change Whenever f=1, the sign (phase) will change

Sample Grover Oracle Circuit

Grover Oracle Circuit Synthesis Thus, the design of Grover search circuits for a given f Thus, the design of Grover search circuits for a given f Is reduced to reversible synthesis Is reduced to reversible synthesis Can be solved optimally by our methods Can be solved optimally by our methods

ROM-based Circuits Desired circuits must alter phase of basis states Desired circuits must alter phase of basis states All bits except one must be restored to input values All bits except one must be restored to input values Previous work studied ROM-based circuits Previous work studied ROM-based circuits Constraint: ROM qubits can never change Constraint: ROM qubits can never change B. Travaglione et al., 2001, B. Travaglione et al., 2001, Theorems + heuristic synthesis algorithms Theorems + heuristic synthesis algorithms Our work: synthesis of pseudo-classical circuits Our work: synthesis of pseudo-classical circuits 3 read-only “ROM” wires that can never change 3 read-only “ROM” wires that can never change 1 wire that can be changed during computation, but must be restored by end 1 wire that can be changed during computation, but must be restored by end 1 wire on which function is computed 1 wire on which function is computed

Synthesis Algorithms Compared Heuristic synthesis of ROM-based circuits Heuristic synthesis of ROM-based circuits Proposed by Travaglione et al, 2001 Proposed by Travaglione et al, 2001 Based on EXOR-sum decomposition (“XOR”) Based on EXOR-sum decomposition (“XOR”) Imposed a restriction: at most one control bit per gate can be on a ROM bit Imposed a restriction: at most one control bit per gate can be on a ROM bit Optimal synthesis (as described earlier) Optimal synthesis (as described earlier) with restriction from Travaglione (“OPT T”) with restriction from Travaglione (“OPT T”) without this restriction (“OPT”) without this restriction (“OPT”)

Sizes of 3+2 ROM-circuits Size XOR OPT T OPT Size XOR OPT T OPT

Discussion of Empirical Results The EXOR-SUM heuristic is sub-optimal The EXOR-SUM heuristic is sub-optimal All methods able to synthesize all 256 fns All methods able to synthesize all 256 fns “OPT T” can synthesize as many as “OPT”: “OPT T” can synthesize as many as “OPT”: B. Travaglione et al., 2001 B. Travaglione et al., 2001 “OPT” results symmetrical about 5-6 gates “OPT” results symmetrical about 5-6 gates Function x requires one fewer gate than 256-x Function x requires one fewer gate than 256-x Explanation yet to be found Explanation yet to be found “XOR” results symmetrical about 13 gates “XOR” results symmetrical about 13 gates

Conclusions Classical reversible circuits as special-case quantum circuits Classical reversible circuits as special-case quantum circuits Existence theorems Existence theorems Reversible De Morgan’s laws Reversible De Morgan’s laws Future research on optimization heuristics Future research on optimization heuristics Algorithm for synthesis of optimal circuits Algorithm for synthesis of optimal circuits Applicable to Grover’s search Applicable to Grover’s search

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