Lecture 1: Introduction to Digital Logic Design CK Cheng Tuesday 4/1/02.

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Presentation transcript:

Lecture 1: Introduction to Digital Logic Design CK Cheng Tuesday 4/1/02

We will cover four major things in this course: - Combinational Logic - Sequential Networks - Standard Modules - System Design

Overall Picture of CS140 Mux Memory ALU Memory Control Subsystem conditions control input

Two Types of Circuits Combinational logic: fi(x) x1. xn y i = f i (x 1,..x n ) xi CLK Sequential Networks 1) Memory 2) Time Steps (Clock) y i t = f i (x 1 t,…x n t, s 1 t, … s n t ) S i t+1 = g i (x 1 t,…,x n t, s 1 t,….s n t )

Part I. Combinational Logic I) Specification II) Implementation III) Different Types of Gates ab + cd abab cdcd e cd ab e (ab+cd)

Example: Adder (counter) Carry Sum Carryout Sums Carry bits

Half Adder a b carry sum Sum = ab’ + a’b Carry = ab Truth Table carry sum abab

Part I. Specification 1)Language 2)Truth Table 3)Boolean Expression 4)Incompletely Specified Function

Example: Full Adder Id a b c in carry sum FA a1b1a1b1 a2b2a2b2 a3b3a3b3 s1s1 s2s2 s3s3 c1c1 c2c2 s4s4 c0c0

Minterm and maxterm Id a b c in carryout a+b+c a+b+c’ a+b’+c a’ b c a’+b+c a b’c a b c’ a b c minterm maxterm

Examples f1(a, b, c in ) = a’bc + ab’c + abc’ + abc f2(a. b. c in ) = (a+b+c)(a+b+c’)(a+b’+c)(a’+b’+c) f1(a, b, c in ) = m3 + m5 + m6 + m7 =  m(3,5,6,7) f2(a, b, c in ) = M0M1M2M4 =  M(0, 1, 2, 4) a’bc = 1 iff (a, b, c) = (0, 1, 1) ab’c = 1 iff (a, b, c) = (1, 0, 1) f1(a,b,c) = 1 iff (a,b,c) = (0,1,1)(1,0,1)(1,1,0)(1,1,1) f2(a+b+c) = 0 iff (a,b,c) = (0,0,0)