Spring 2007EE130 Lecture 32, Slide 1 Lecture #32 OUTLINE The MOS Capacitor: Capacitance-voltage (C-V) characteristics Reading: Chapter 16.4

Spring 2007EE130 Lecture 32, Slide 2  S and W vs. V G (p-type Si) V FB VTVT VGVG 2F2F S:S: accumulationdepletioninversion 0 VGVG accumulationdepletioninversion 0 W:W: V FB VTVT

Spring 2007EE130 Lecture 32, Slide 3 Total Charge Density in Si, Q s VGVG accumulationdepletioninversion 0 V FB VTVT VGVG accumulationdepletioninversion 0 V FB VTVT VGVG accumulation depletioninversion 0 V FB VTVT VGVG accumulationdepletioninversion 0 V FB VTVT Q inv slope = -C ox

Spring 2007EE130 Lecture 32, Slide 4 MOS Capacitance Measurement v ac i ac C-V Meter Si GATE MOS Capacitor V G is scanned slowly Capacitive current due to v ac is measured

Spring 2007EE130 Lecture 32, Slide 5 MOS C-V Characteristics (p-type Si) VGVG accumulationdepletioninversion V FB VTVT Q inv slope = -C ox VGVG accumulationdepletioninversion V FB VTVT C C ox Ideal C-V curve:

Spring 2007EE130 Lecture 32, Slide 6 Capacitance in Accumulation (p-type Si) As the gate voltage is varied, incremental charge is added/subtracted to/from the gate and substrate. The incremental charges are separated by the gate oxide. M O S QQ Q  Q -Q C ox

Spring 2007EE130 Lecture 32, Slide 7 Flat-Band Capacitance At the flat-band condition, variations in V G give rise to the addition/subtraction of incremental charge in the substrate, at a depth L D L D is the “extrinsic Debye Length” –characteristic shielding distance, or the distance where the electric field emanating from a perturbing charge falls off by a factor of 1/ e C ox C Debye

Spring 2007EE130 Lecture 32, Slide 8 Capacitance in Depletion (p-type Si) As the gate voltage is varied, the width of the depletion region varies.  Incremental charge is effectively added/subtracted at a depth W in the substrate. M O S QQ Q  Q -Q C ox W C dep

Spring 2007EE130 Lecture 32, Slide 9 Capacitance in Inversion (p-type Si) CASE 1: Inversion-layer charge can be supplied/removed quickly enough to respond to changes in the gate voltage.  Incremental charge is effectively added/subtracted at the surface of the substrate. M O S QQ  Q C ox WTWT Time required to build inversion-layer charge = 2N A  o /n i, where  o = minority-carrier lifetime at surface

Spring 2007EE130 Lecture 32, Slide 10 Capacitance in Inversion (p-type Si) CASE 2: Inversion-layer charge cannot be supplied/removed quickly enough to respond to changes in the gate voltage.  Incremental charge is effectively added/subtracted at a depth W T in the substrate. M O S QQ  Q WTWT C ox C dep

Spring 2007EE130 Lecture 32, Slide 11 C ox gate p-type Si - WTWT AC DC C ox gate p-type Si C ox gate p-type Si C dep W C ox gate p-type Si WTWT N + DC and AC Accumulation:Depletion: Inversion: Supply of Substrate Charge (p-type Si) C dep,min Case 1Case 2

Spring 2007EE130 Lecture 32, Slide 12 Capacitor vs. Transistor C-V (or LF vs. HF C-V) p-type Si: VGVG accumulationdepletioninversion V FB VTVT C MOS transistor at any f, MOS capacitor at low f, or quasi-static C-V MOS capacitor at high f C min C max =C ox C FB

Spring 2007EE130 Lecture 32, Slide 13 The quasi-static C-V characteristic is obtained by slowly ramping the gate voltage (< 0.1V/s), while measuring the gate current I G with a very sensitive DC ammeter. C is calculated from I G = C·(dV G /dt) Quasi-Static C-V Measurement VGVG accumulationdepletioninversion V FB VTVT C C max =C ox p-type Si: C min C FB

Spring 2007EE130 Lecture 32, Slide 14 Deep Depletion If V G is scanned quickly, Q inv cannot respond to the change in V G. The increase in substrate charge density Q s must then come from an increase in depletion charge density Q dep  depletion depth W increases as V G increases  C decreases as V G increases VGVG V FB VTVT C C ox C min