S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 34: Design Methods (beyond Tanner Tools) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Maxfield/Newnes]

S. Reda EN160 SP’07 Stage I. IC Design, Verification, and Test Specification Design schematics Ideas HDL (Verilog/VHDL) C-based design (SystemC) Test-structure Insertion Synthesis library gate-level design simulation/ verification

S. Reda EN160 SP’07 Stage II. IC Physical Implementation Flow Floorplanning/placement repeater insertion clock tree synthesis P/G network / routing metal fill insertion DRC/LVS gate-level circuit reticles/masks Timing analysis Parasitic extraction Power analysis Signal Integrity mask generation / OPC Custom/Application Specific IC (ASIC) FPGAs Floorplanning/placement routing download

S. Reda EN160 SP’07 Stage III. Fabrication and Packaging reticles fabricate wafer Test dies dice and package the good ones chips

S. Reda EN160 SP’07 Stage I. IC Design, Verification, and Test Specification Design schematics Ideas HDL (Verilog/VHDL) C-based design (SystemC) Test-structure Insertion Synthesis Library gate-level design verification

S. Reda EN160 SP’07 Design Entry

S. Reda EN160 SP’07 Functional Simulation Make sure your design is logically correct.

S. Reda EN160 SP’07 Synthesis Synthesis transforms HDL to gates Synthesis has to be “smart”

S. Reda EN160 SP’07 Verification We cannot try all possible input combinations to check our design How can we verify that our synthesizer is correct? Imagine you are designing a traffic light controller, how can you guarantee that the light will not be simultaneously green for both directions? Formal verification uses mathematical techniques to verify certain properties of your design.

S. Reda EN160 SP’07 Stage II. IC Physical Implementation Flow Floorplanning/placement repeater insertion clock tree synthesis P/G network / routing metal fill insertion DRC/LVS gate-level circuit reticles/masks Timing analysis Parasitic extraction Power analysis Signal Integrity mask generation / OPC Custom/Application Specific IC (ASIC) FPGAs Floorplanning/placement routing download

S. Reda EN160 SP’07 Fast timing analysis using static timing analysis (STA) I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 O1O1 O2O2 What is the worst delay of this circuit without regard to the dynamic input patterns? What are the critical path(s) that lead to this delay?  perhaps timing can be improved if we adjust them C17 from ISCAS’85 benchmarks

S. Reda EN160 SP’07 Floorplanning and placement Floorplanning (chip outlining) is a small scale 2-D assignment problem  determines positions for large blocks of logic/memory rows I/O pads Placement of standard cells is a large-scale 2-D assignment problem  determines positions for thousands/millions of standard cells [illegal placement] [legal placement]

S. Reda EN160 SP’07 minimize demand on metal resources and reduces power skew can lead to setup/hold times violations Clock tree synthesis Clock net(s)  delivers the periodic generated clock signal to FFs Design objectives: Zero-or prescribed skew minimum wirelength minimize buffers for signal integrity FF data clock extra delay [Kahng et al., TCAS’92] Minimum wirelength zero-skew tree for 64 FFs minimize #buffers and maintain SI

S. Reda EN160 SP’07 Buffering (repeater insertion) for timing and signal integrity source sink What is the minimum number of repeaters to meet timing on this net? The situation is complicated in case of multi-pin nets: Repeater estimation for Itanium Repeater Stations

S. Reda EN160 SP’07 Design and analysis of power supply networks [Blaauw et al., DAC98] PowerPC 750 power grid PowerPC 750 IR-drop map Power supply network delivers Vdd/Gnd signals to all components. Main challenges: 1. IR drop: voltage at delivery point is degraded than the ideal voltage performance drop signal integrity problems 2. electromigration

S. Reda EN160 SP’07 Routing pin p 1 pin p 2 Do you want this to happen to a net that belongs to the critical path?! Objective: determine routes (tracks, layers, and vias) for each net such that the total wirelength is minimized.  Be careful with routing critical nets and clock nets cell congestion

S. Reda EN160 SP’07 Routing and parasitic extraction source sink map to layers create vias  Multi-pin nets add more complexity in routing  After all routes are determined, you can calculate the parasitic capacitance between each wire and its neighbors

S. Reda EN160 SP’07 Fill insertion Wafer Wafer carrier Rotating platen Polishing slurry Slurry dispenser Polishing pad Downforce CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers Remember the DRC violations from L-Edit! How can metal fill insertion helps in smoothing surfaces? [(animation is not technically correct!] [Photos are form Quirk/Serda] Features Post-CMP ILD thickness Area fill features

S. Reda EN160 SP’07 Mask preparation and resolution enhancement techniques (RET) original layout MEBES fractured layout fractured layout into polygons (rectangles and trapezoids) GDSII [mask writer uses electron beam for printing patterns]

S. Reda EN160 SP’07 Mask preparation and resolution enhancement techniques (RET) Light source 193nm 130nm feature [Schellenberg, IEEE Spectrum’03]

S. Reda EN160 SP’07 Stage III. Fabrication and Packaging reticles fabricate wafer Test dies dice and package the good ones chips

S. Reda EN160 SP’07 Fabrication and Test Testing –Functional (yield) How many circuits work (have no defects)? –Delay/Power (parametric yield) What is the speed and power of the ones that work? percentage of chips Manufacturers speed bin their chips and sell them according to their performance 3.0Ghz 3.2Ghz 3.1Ghz F 2.9Ghz F

S. Reda EN160 SP’07 Dicing and packaging wafer dice reticles

S. Reda EN160 SP’07 Packaging choices

S. Reda EN160 SP’07 Summary Overview of IC design flow We are done with main lectures We meet in exactly one week on May 4 th to give your project presentations