Latches and Flip-Flops Discussion D4.1 Appendix J

Latches and Flip-Flops Latches –SR Latch –Clocked SR Latch –D Latch Flip-Flops –Edge-Triggered D Flip-Flop

Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only on current input but also on past input values –Need some type of memory to remember the past input values

Cross-coupled Inverters State 1 State 2

Latches and Flip-Flops Latches –SR Latch –Clocked SR Latch –D Latch Flip-Flops –Edge-Triggered D Flip-Flop

SR Latch S' R' Q Q' X Y nand

X Y nand SR Latch S' R' Q Q'

X Y nand SR Latch S' R' Q Q'

X Y nand 1 0 Set SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store 0 1 Reset SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store 0 1 Reset SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 Q 0 ' SR Latch S' R' Q Q'

X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 Q 0 ' To close or lock with or as if with a latch, To catch or fasten SR Latch S' R' Q Q'

R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '1' and R = '0' then Q <= '1'; elsif S = '0' and R = '1' then Q <= '0'; end if; end process; end rslatch; R-S Latch R S Q Active HIGH

R-S Latch -- Active High

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '0' and R = '1' then Q <= '1'; elsif S = '1' and R = '0' then Q <= '0'; end if; end process; end rslatch; R-S Latch R S Q Active LOW

R-S Latch -- Active Low

How can you make this R-S latch from gates? R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

R S Q Q R-S Latch R S Q Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0). Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0). R SQ Q = R'Q + R'S + SQ store set reset store

R S Q Q store set reset store R-S Latch R S Q RS Latch Q = R'Q + R'S + SQ

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatchgates is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatchgates; architecture rslatchgates of rslatchgates is signal Q1: std_logic; begin Q1 <= (not R and Q1) or (not R and S) or (S and Q1); Q <= Q1; end rslatchgates; Q1

Latches and Flip-Flops Latches –SR Latch –Clocked SR Latch –D Latch Flip-Flops –Edge-Triggered D Flip-Flop

Clocked SR Latch S' R' Q Q' S R CLK S R CLK S' R' Q Q' Q 0 Q 0 ' Store Reset Set Disallowed X X Q 0 Q 0 ' Store

Latches and Flip-Flops Latches –SR Latch –Clocked SR Latch –D Latch Flip-Flops –Edge-Triggered D Flip-Flop

D Latch D EN Q Q follows D when EN is high, and remains unchanged when EN is low..

library IEEE; use IEEE.STD_LOGIC_1164.all; entity dlatch is port( D : in STD_LOGIC; EN : in STD_LOGIC; Q : out STD_LOGIC ); end dlatch; architecture dlatch of dlatch is begin process(D,EN) begin if EN = '1' then Q <= D; end if; end process; end dlatch; D Latch D EN Q

D Latch

Q Q' EN D S' R' S R S R EN Q Q' Q 0 Q 0 ' Store Reset Set Disallowed X X 0 Q 0 Q 0 ' Store X 0 Q 0 Q 0 ' D EN Q Q'

D Latch X 0 Q 0 Q 0 ' D EN Q Q' Note that Q follows D when EN in high, and is latched when EN goes to zero. Q Q' EN D S' R' S R

Latches and Flip-Flops Latches –SR Latch –Clocked SR Latch –D Latch Flip-Flops –Edge-Triggered D Flip-Flop

D Flip-Flop X 0 Q 0 Q 0 ' D clk Q Q' D gets latched to Q on the rising edge of the clock. Positive edge triggered if rising_edge(clk) then Q <= D; end if; Behavior clk D Q Q'

Master-Slave D Flip-Flop

Recall the SR Latch X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 Q 0 ' S' R' Q Q'

Edge-triggered D Flip-flop

Edge-triggered D Flip-flop with asynchronous set and reset

D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

Spartan 3 CLB slices