Operating Systems Béat Hirsbrunner Main Reference: William Stallings, Operating Systems: Internals and Design Principles, 6 th Edition, Prentice Hall 2009 University of Fribourg Autumn Semester September 2010 Lecture 2. Background: Computer System Overview

1 1.1 Basic Elements

2 1.2 Processor Registers User-Visible Registers  Data registers  Address register incl. index register, segment pointer, stack pointer Control and status Registers  Program counter (PC)  Instruction register (IR)  Program status word (PSW)  Condition codes (flags) Remark about the design of registers  Should provide hardware support for particular OS features Memory protection Switching between user programs Allocation of “control information” between registers and main memory

3 1.3 Instruction Execution Four categories of instructions Processor Memory Processor I/O Data Processing Control (for conditionals or loops) Special control instruction DMA (direct memory access) : main memory I/O

4 1.3 Instruction Execution

5 List of opcodes 0x1 = Load AC from Memory 0x2 = Store AC to Memory 0x5 Add to AC from Memory

6 1.4 Interrupts: most common classes

7 1.4 Interrupts: control flow

8 1.4 Interrupts: control transfer The Interrupt Handler program is generally part of the operating system

9 1.4 Interrupts: instruction cycle

Interrupts: efficiency (cf. Figs 1.5a, 1.5b) With interrupts I/O operations (often 1000 or more cycles) are done in parallel to the exection of program instructions I/O CPU cycles (in general 1 to 10)

Interrupts: efficiency (cf. Figs 1.5a, 1.5c) I/O CPU cycles (in general 1 to 10)

Interrupts: processing cf. Fig. 1.11a cf. Fig. 1.11b

Interrupts: processing (a) Step 6 of Fig. 1.10(b) Step 8 of Fig. 1.10

Interrupts: multiple interrupts

Interrupts: multiple interrupts Priority 2Priority 5 Priority 4 Time arrival of the interrupts: printer t=10, comm. t=15, disk t=20

The Memory Hierarchy

The Memory Hierarchy: performance Remark: hit rate are often around 90%, due to the “locality of references”, see also fig. 1.24

Cache Memory

Cache Memory: structure

Cache Memory: operations

I/O Communication Techniques

22 Appendix 1A: performance of 2 level memories

23 Appendix 1A: performance of 2 level memories

24 Appendix 1A: performance of 2 level memories

25 Appendix 1A: performance of 2 level memories

26 Appendix 1A: performance of 2 level memories

27 Appendix 1A: performance of 2 level memories

28 Appendix 1A: performance of 2 level memories see also fig. 1.15

29 Appendix 1B: Procedure Control

30 Appendix 1B: Procedure Control

31 Appendix 1B: Procedure Control

32 Appendix 1B: Procedure Control