Evaluation of Branch Predictors Using High-density-branch Programs Fang Pang MEng. Lei Zhu MEng. Electrical and Computer Engineering Department University.

Slides:

Advertisements

Similar presentations

Project : Phase 1 Grading Default Statistics (40 points) Values and Charts (30 points) Analyses (10 points) Branch Predictor Statistics (30 points) Values.

Advertisements

Branch prediction Titov Alexander MDSP November, 2009.

Chapter 1. Basic Structure of Computers

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.

5.5 Encoders A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes.

Give qualifications of instructors: DAP

CDA 3100 Recitation Week 10.

Princess Sumaya University

9-6 The Control Word Fig The selection variables for the datapath control the microoperations executed within datapath for any given clock pulse.

MICRO-PROCESSORS Objective To demonstrate How a Microprocessor do common calculations and the process involved in it. The type of calculations in which.

1.Calculate number of events by searching for event in assembly file or analytical model. 2.Validate the numbers from step one with a simulator. 3.Compare.

CPT 310 Logic and Computer Design Instructor: David LublinerPhone Engineering Technology Dept.Cell

Branch Prediction in SimpleScalar

Maximum Likelihood Sequence Detection (MLSD) and the Viterbi Algorithm

ENGIN112 L4: Number Codes and Registers ENGIN 112 Intro to Electrical and Computer Engineering Lecture 4 Number Codes and Registers.

Glenn Reinman, Brad Calder, Department of Computer Science and Engineering, University of California San Diego and Todd Austin Department of Electrical.

ELEC 7250 Term Project Presentation Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL.

7/2/ _23 1 Pipelining ECE-445 Computer Organization Dr. Ron Hayne Electrical and Computer Engineering.

Source Coding Hafiz Malik Dept. of Electrical & Computer Engineering The University of Michigan-Dearborn

4-6 3x3 Matrices, Determinants, & Inverses

DIGITAL COMPONENTS By Sohaib.

High Throughput Compression of Double-Precision Floating-Point Data Martin Burtscher and Paruj Ratanaworabhan School of Electrical and Computer Engineering.

Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic.

Korea Univ B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors 컴퓨터 · 전파통신공학과 최병준 1 Computer Engineering and Systems Group.

Computer Programming Basics Assistant Professor Jeon, Seokhee Assistant Professor Department of Computer Engineering, Kyung Hee University, Korea.

Statistical Modeling with SAS/STAT Cheng Lei Department of Electrical and Computer Engineering University of Victoria April 9, 2015.

Eng. Mohammed Timraz Electronics & Communication Engineer University of Palestine Faculty of Engineering and Urban planning Software Engineering Department.

Lecture 8: Processors, Introduction EEN 312: Processors: Hardware, Software, and Interfacing Department of Electrical and Computer Engineering Spring 2014,

The Central Processing Unit (CPU) and the Machine Cycle.

Coding Theory Efficient and Reliable Transfer of Information

Dr. Sudharman K. Jayaweera and Amila Kariyapperuma ECE Department University of New Mexico Ankur Sharma Department of ECE Indian Institute of Technology,

CO UNIT-I. 2 Multiplexers: A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has.

Error control coding – binary linear codes Background material for linear error control codes.

A New Operating Tool for Coding in Lossless Image Compression Radu Rădescu University POLITEHNICA of Bucharest, Faculty of Electronics, Telecommunications.

CPS3340 COMPUTER ARCHITECTURE Fall Semester, /3/2013 Lecture 9: Memory Unit Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL.

VLSI AND INTELLIGENT SYTEMS LABORATORY 12 Bit Hamming Code Error Detector/Corrector December 2nd, 2003 Department of Electrical and Computer Engineering.

Functional Modeling.

NoSQL Cheng Lei Department of Electrical and Computer Engineering University of Victoria Mar 05, 2015.

HOW COMPUTERS WORK THE CPU & MEMORY. THE PARTS OF A COMPUTER.

More Intro MIPS Computer Organization I 1 September 2009 © McQuain, Feng & Ribbens Machine Language But, how is all of this driven? Machine.

Department of Electronic & Electrical Engineering Seven segment display Subroutines.

Department of Electronic & Electrical Engineering Lecture 2 ● Introduction to IO ● Using a subroutine ● Driving a 7seg display.

Multiplexors Decoders  Decoders are used for forming separate signals for different combination of input signals.  The multiplexer circuit is a digital.

Convolutional Coding In telecommunication, a convolutional code is a type of error- correcting code in which m-bit information symbol to be encoded is.

Elements of Datapath for the fetch and increment The first element we need: a memory unit to store the instructions of a program and supply instructions.

Software. Introduction n A computer can’t do anything without a program of instructions. n A program is a set of instructions a computer carries out.

C OMBINATIONAL L OGIC D ESIGN 1 Eng.Maha AlGubali.

Decoders A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence.

Introduction to Algorithm Complexity Bit Sum Problem.

Character coding schemes

Error Correcting Code.

Data Encoding Characters.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Decoders.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.

Design of the Control Unit for Single-Cycle Instruction Execution

EE345: Introduction to Microcontrollers Memory

Functional Units.

Stephen Hines, David Whalley and Gary Tyson Computer Science Dept.

Design of the Control Unit for One-cycle Instruction Execution

Detailed Analysis of MiBench benchmark suite

Introduction to Computer Architecture

Topic 5: Processor Architecture Implementation Methodology

Topic 5: Processor Architecture

Distributed Compression For Binary Symetric Channels

8-6 The Control Word The selection variables for the datapath control the microoperations executed within datapath for any given clock pulse Fig

Arithmetic Circuits.

Gang Luo, Hongfei Guo {gangluo,

Introduction to Computers

Presentation transcript:

Evaluation of Branch Predictors Using High-density-branch Programs Fang Pang MEng. Lei Zhu MEng. Electrical and Computer Engineering Department University of Alberta November, 2002

Introduction In this project, we are going to evaluate different branch predictors for high-density-branch programs. A C code for Binary (6,4) encoder and decoder is used as example program. 1. Simplescalar tool will be used as the simulation tool. 2. The effectiveness of different types of branch predictors is observed. And the effect of the size of predictor is observed.

Example Program The Binary (6,4) encoder takes 4-bit source words as inputs, reads though the lookup table stored in the memory, finds out the corresponding 6-bit code words and exports code words. All code words are added by random noise and sent to Binary (6,4) decoder. The Binary (6,4) decoder takes these 6-bit code words as inputs, reads through the lookup table, finds out the corresponding 4-bit source words and exports source words. And it treats it as an error if the corresponding source word can’t be found in the lookup table. At the end of process, it calculates the number of errors and the error rate. This program contains high-density branches. Most of them are random conditon branches.

Project Description Taken branch, bimodal predictor, 2-level adaptive predictor and combined predictor are evaluated. Different size of predictors are compared. Multiple function units and multiple ports of memory are used to support wide issue. Different caches for data and instructions are used.

Simulation Sim-Outorder will be used to evaluate performance of different branch predictors. Different size predictors will be tested and compared.

Goal Find out the best branch predictor for this example program. Find out the relationship between the size of predictor and its performance.

Question ??? Thanks!