Dual-Camera Motion Tracking Recorder (DCMTR) Group #1 Lee Estep Philip Robertson Andy Schiestl Robert Tate

Objectives n Implement Modules and Interfaces n Update Interfaces for Second Camera n Develop Tracking Algorithm n Combine Interfaces into One System n Develop GUI for PC Interface n Deliverable – Security Camera System

Background n Autonomous Tracking System (ATS) from Spring 1999 n Foundation for the DCMTR

Background n Electronic Book Project from Spring 1999 n Guide for the IDE Hard Drive implementation n Used for basic understanding due to different constraints

System Design n Design 1: Three FPGA System n Design 2: Two FPGA and a Micro-controller System

System Design n Design 3: One FPGA System n Design 4: Two FPGA System FPGA XC4028E Hard Drive, Camera Interface, Parallel port, and Servo Control Camera and Servos 1 Camera and Servos 2 Hard Drive

Final Design Schematic Xilinx XC4010E (FPGA #2) ServoSet2 ServoSet1 64K SRAM IDE Interface PC Interface Servo Control FPGA Interface Memory Control IDE Hard Drive PC (Only needed for playback) QuickCam2 QuickCam1 64K SRAM Xilinx XC4010E (FPGA #1) Camera Interface Memory Control Algorithm FPGA Interface

Algorithm Design n Design 1 – Extend ATS Algorithm to support two cameras n Design 2 – Modify Design 1 to compare two images of the same scene instead of analyzing one n Design 3 – Extend Design 2 to compensate for camera motion

Components: Algorithm n Algorithm FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: QuickCams n Two Connectix QuickCams n Camera Interface FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: Servo Control n Servo Control n Four Servo Motors FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: Memory Control n FPGA 1 Memory Control n FPGA 2 Memory Control n 64K SRAM FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: FPGA Interface n Each FPGA has an interface for communication with the other FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: Hard Drive n IDE Hard Drive n IDE Interface FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Components: PC Interface n PC n PC Interface FPGA 2 Servos 2 Servo 1 SRAM IDE Interface PC IF Servo Ctl FPGA IF Memory Control HDD PC QC 2 QC 1 SRAM FPGA 1 QC IF MemCtl Algorithm FPGA IF

Component Cost

Member Responsibilities

References n Texas Instruments – n Digi-Key – n Xilinx – n Winbond – n Vantec – n CPSC 483 IDE Interface for E-Book Project Spring 1999 – n CPSC 483 Autonomous Tracking Unit Project Spring 1999 –