Michigan State University 6/28/2015 1 L2 I/O Transfer James T. Linnemann Michigan State University Trigger Meeting February 20, 1998.

Slides:

Advertisements

Similar presentations

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.

Advertisements

Context Diagram Yong Choi BPA CSUB.

IO Interfaces and Bus Standards. Interface circuits Consists of the cktry required to connect an i/o device to a computer. On one side we have data bus.

Control Unit Implemntation

Michigan State University 4/15/ Simulation for Level 2 James T. Linnemann Michigan State University NIU Triggering Workshop October 17, 1997.

J. Linnemann, MSU 4/15/ Global L2 Outputs (and inputs) James T. Linnemann Michigan State University NIU Trigger Workshop October 17, 1997.

Bob Hirosky, UVa 7/27/01  Level 2 Processor Status  Bob Hirosky The University of Virginia 

USLP Interface and Processing between Coding & Sync Sub-layer and Data Link Protocol Sub-layer.

DH2T 34 Computer Architecture 1 LO2 Lesson Two CPU and Buses.

PXL RDO System Requirements And meeting goals 11/12/2009BNL_CD-1_SENSOR_RDO - LG1.

A Gigabit Ethernet Link Source Card Robert E. Blair, John W. Dawson, Gary Drake, David J. Francis*, William N. Haberichter, James L. Schlereth Argonne.

DIRECT MEMORY ACCESS CS 147 Thursday July 5,2001 SEEMA RAI.

Run IIb L1CAL TCC Philippe Laurens MSU 9-Feb-2006.

L2 Trigger Connections V4.2 Page 1 of 3February 1, 1999 Jerry Blazey NIU Si Trker Fi-Glink 1. 3Gb/s, 20-bit L2STT (In Design) L1 CFT Cu-AMCC 1.4Gb/s Fi-Glink.

Michigan State University 6/20/ L2 Status James T. Linnemann Michigan State University DØ Collaboration Meeting April 3, 1998.

J. Linnemann, MSU 6/21/ Agenda L2 monitoring and readout Jim Linnemann 20 min Magic Bus Transceiver Dan Edmunds 20 min Plans for the GL2 Card Drew.

Michigan State University 7/12/ The Standard L2 Crate James T. Linnemann Michigan State University FNAL L2 Workshop December 19, 1997.

CHAPTER 6 FILE PROCESSING. 2 Introduction  The most convenient way to process involving large data sets is to store them into a file for later processing.

Ethernet. Ethernet [DEC, Intel, Xerox] 1-persistent, CSMA-CD with Binary Exponential Backoff Manchester encoding.

MBT Alpha SFOSLIC SFOCIC Front Ends L1 (SCL) MBT Alpha SLIC Example: Test Stand Shadowing a SLIC Test Stand A.Maciel L2mu NIU Target Shadow MBT/Alpha outputs.

Input / Output CS 537 – Introduction to Operating Systems.

Advanced File Processing

ECE 526 – Network Processing Systems Design Network Processor Architecture and Scalability Chapter 13,14: D. E. Comer.

Chapter 10: Input / Output Devices Dr Mohamed Menacer Taibah University

ZTF Server Architecture Roger Smith Caltech

Hardware Design of High Speed Switch Fabric IC. Overall Architecture.

Fundamental File Structure Concepts & Managing Files of Records

Segmentation & O/S Input/Output Chapter 4 & 5 Tuesday, April 3, 2007.

Spring EE 437 Lillevik 437s06-l8 University of Portland School of Engineering Advanced Computer Architecture Lecture 8 Project 3: memory agent Programmed.

© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Principles of I/0 hardware.

DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK

CS 342 – Operating Systems Spring 2003 © Ibrahim Korpeoglu Bilkent University1 Input/Output CS 342 – Operating Systems Ibrahim Korpeoglu Bilkent University.

PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout.

Advanced File Processing. 2 Objectives Use the pipe operator to redirect the output of one command to another command Use the grep command to search for.

Chapter Five Advanced File Processing Guide To UNIX Using Linux Fourth Edition Chapter 5 Unix (34 slides)1 CTEC 110.

Chapter Five Advanced File Processing. 2 Objectives Use the pipe operator to redirect the output of one command to another command Use the grep command.

Nikos Varelas University of Illinois at Chicago L2Cal Group at UIC: Mark Adams Bob Hirosky Rob Martin Nikos Varelas Marc Buehler (graduate student) James.

CPT Week, April 2001Darin Acosta1 Status of the Next Generation CSC Track-Finder D.Acosta University of Florida.

Uli Schäfer 1 JEM Status and plans Hardware -JEM1 -Status Firmware -Algorithms -Status Plans.

Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.

FNAL STT Meeting  H.Evans 8/9/99 Communication & Control H.EvansColumbia U. Overview of FRC Functions:  Road Info STCs,TFCs –Device Independent Data.

Data Representation Conversion 24/04/2017.

Chapter Five Advanced File Processing. 2 Lesson A Selecting, Manipulating, and Formatting Information.

Michigan State University 11/26/ Overview of Level 2 James T. Linnemann Michigan State University Level 2 Review Feb 6, 1999.

ATLAS Trigger / current L1Calo Uli Schäfer 1 Jet/Energy module calo µ CTP L1.

Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.

SoLiD/PVDIS DAQ Alexandre Camsonne. DAQ limitations Electronics Data transfer.

L2mu System - Status SLICs Track Finding (main data processing) Next: SLIC Upstream and Downstream DONE UPSTREAM; CICs and SFOs CIC crate; hooked into.

IT3002 Computer Architecture

Basic Elements of Processor ALU Registers Internal data pahs External data paths Control Unit.

J. Linnemann, MSU 2/12/ L2 Status James T. Linnemann MSU PMG September 20, 2001.

1 Level 1 Pre Processor and Interface L1PPI Guido Haefeli L1 Review 14. June 2002.

Bob Hirosky L2  eta Review 26-APR-01 L2  eta Introduction L2  etas – a stable source of processing power for DØ Level2 Goals: Commercial (replaceable)

Amsterdam, Oct A. Cotta Ramusino, INFN Ferrara 1 EUDRB: status report and plans for interfacing to the IPHC’s M26 Summary: EUDRB developments.

1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.

PHENIX DAQ RATES. RHIC Data Rates at Design Luminosity PHENIX Max = 25 kHz Every FEM must send in 40 us. Since we multiplex 2, that limit is 12 kHz and.

CMX: Update on status and planning Yuri Ermoline, Wojciech Dan Edmunds, Philippe Laurens, Chip Michigan State University 7-Mar-2012.

The Data Handling Hybrid Igor Konorov TUM Physics Department E18.

1 load [2], [9] Transfer contents of memory location 9 to memory location 2. Illegal instruction.

SVD FADC Status Markus Friedl (HEPHY Vienna) Wetzlar SVD-PXD Meeting, 5 February 2013.

Serial Communications

Digital readout architecture for Velopix

CMS EMU TRIGGER ELECTRONICS

Guide To UNIX Using Linux Third Edition

Direct Memory Access Introduction

Communication & Control

PLC Hardware Components.

Debugging Debug environments Debug via serial

Variable Length Data and Records

New DCM, FEMDCM DCM jobs DCM upgrade path

Presentation transcript:

Michigan State University 6/28/ L2 I/O Transfer James T. Linnemann Michigan State University Trigger Meeting February 20, 1998

Michigan State University 6/28/ L3 MPMMPM WorkerWorker AdminAdmin MBTMBT Dec Alpha (Unix) VME Current Status JTL, MSU 12/18/ TCC VBDVBD Inputs MBus SCL Outputs to Global (preprocessors only) L2 Answer L2 HWFW (Global only) 8 VME slots minimum

Michigan State University 6/28/ L2 Global Inputs l L2 Global Inputs via MBT card l MBT: propose Fiber 160 Mb/s Requires SLIC have one Fiber output Question: is SCL Fanout Fiber or Copper l Advantages: Simpler to set up than copper (balancer, transformer Less fussy to make work separation of grounds (if move out of MCH)

Michigan State University 6/28/ L2 Input Fiber, continued l Disadvantages of Fiber: FIC needs fiber to serve MBT, copper for SLIC more expensive: $60/channel or so –including cable/fiber? –Cost for both ends or one? beware of finger prints patch panel more complex/costly –needed to re-cable if L2 in Fixed Counting House and MCH moves

Michigan State University 6/28/ Fiber Input Converter l Inputs: l only g-link transfer from L1 CFT/PS assuming 8/10 or 16/20 encoding for integrity l g-link: Speed requirements of STT input recycle engineering of VRB inputs (STT needs raw data) l Outputs (Cypress) 160 Fiber (MBT) 160 Copper (SLIC)

Michigan State University 6/28/ L1 CFT Outputs to FIC l Begin and End Event as g-link Symbols not as values of data l Not in Gray code l Padded to 16 B l 3B Crossing number (to match L1 accept) l Header and Trailer consistent with L2G input specs l PS data on fibers separate from CFT fibers l Bytes produced so no swapping on FIC needed?

Michigan State University 6/28/ Byte (non-) swapping l Source’s responsibility; NONE on MBT card l Send bytes to Cypress in order such that when assembled in Alpha, they have specified order (B1, B2, B3, B4) l Will provide “final” spec so multi-byte quantities (3B crossing number, 2B eta, etc) come out right in Alpha l Do L1CFT 2B quantities have fields crossing Byte boundaries?

Michigan State University 6/28/ L2G Header/trailer l 12B Header, 4B Trailer l Tradeoff: 4B Header word fixed vs. 4B Trailer = one 4B Header word l Opinions?

Michigan State University 6/28/ L2G Header, Trailer Matched H1: Length (1B), Format # (2B), Object Length(1B) H2: Source(1B),Rotation(2B), Bunch(1B) H3: Status(1B),Version(1B),Switches(1B),Nobj(1B) Trailer = H2

Michigan State University 6/28/ L2G Header, Fixed Word H1: Length (1B), Format # (2B), Object Length(1B) H2: Nobj(1B),Rotation(2B), Bunch(1B) H3: Source(1B),Status(1B),Version(1B),Switches(1B) Trailer:Source(1B),Rotation(2B), Bunch(1B)

Michigan State University 6/28/ FIC for raw data? l More complex beast! Gray Code conversion required Need to generate/resynch crossing number –bus to all channels Need to generate header/trailer need to pad to 16B? REQUEST g-link start/end symbols –else recognition task needed to count events in buffers l Considerable Escalation over L1 FIC Defer design until proven to be needed