A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

Introduction Trends in Mask Cost –Mask data preparation is a serious bottleneck due to the heavily applied RET Figure count explodes as dimensions shrink Data volume for a single mask layer can approach 100GB

Introduction (Cont.) Trends in Mask Cost (Cont.) –Mask set cost increases at an accelerated rate with RET application as the primary driver Need to determine how best to apply RETs to standard cell libraries to minimize mask cost

Introduction (Cont.) Cost of correction problem –Entire layout is corrected uniformly with the same effort in current OPC technologies –Less aggressive use of OPC results in lowered cost through shorter mask write time and higher mask yield –Determine the level of correction for each feature without sacrificing the prescribed selling point delay: minimum cost of correction (MinCorr)

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

Cost of Correction Methodology Yield closure flow –Assume different levels of OPC can be independently applied to any gate in the design with corresponding L and cost –Compute selling point delay at each primary output

Mapping MinCorr to Traditional Performance Optimization Assume standard deviations of the gate-delays are additive: –Allows the use of STA instead of SSTA –Likely to be pessimistic: Results from extreme value theory can be used to increase likelihood of the selling point delay being overestimated. Construct yield libraries in a similar fashion as timing libraries. –Allows the use of commercial synthesis tools.

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

Experimental Testbed Three level OPC correction Yield aware library characterization –Based on a reduced TSMC.lib (containing 28 cells) generate new library files corresponding to each level of OPC correction Mask cost model –Figure count given as a multiple of that found in a non-OPC layout Synthesis tool –We use Synopsys DC, to solve the MinCorr problem –Enables us to try out interesting variant problems such as cost constrained selling point delay minimization

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

Results and discussion alu128 and c7552 are 2000 gate combinational designs. Little (about 4%) variation in selling point delay from max- corrected to min-corrected versions of the design –Small gate delay change for these OPC levels –We assume no input cap. Change with variation. With second order effects are considered, changes in selling point delay are expected to be larger

Outline Introduction –Trends in mask cost –Design for value –The cost of correction problem Cost of Correction Methodology –Mapping the MinCorr problem to conventional performance optimization Experimental Testbed –Yield aware library characterization –Synthesis tool Results and discussion Conclusions and ongoing work

It is possible to reduce the total cost of OPC while still meeting yield and cycle time targets by making OPC design aware Conventional gate-sizing methods can be easily modified to solve the MinCorr cost of correction problem. We have given a recipe to use an industry standard synthesis tool to perform the job OPC might be more of a manufacturability issue rather than a performance or yield issue With sizing based optimizations and selective OPC, we can save up to 77% cost compared to aggressive OPC, without increasing the selling point delay. Design performance oblivious RET techniques suffer from large cost overheads

Conclusions and ongoing work Statistical Static Timing Analysis based correction: use SSTA to validate the sizing results and heuristically “fix” the sizing solution: –Gates that fanout to a large number of critical paths are good candidates for correction –Gates that fanout to a small number of critical paths are good candidates for decorrection Alternative approaches to correction –Transistor sizing instead of gate-sizing –Cost based delay budgeting methods More accurate correction –Input slew awareness in the yield libraries and including interconnect in the analysis –Consider dependence of gate input capacitance on L variation in the yield libraries