Fred Chen & Lixin Su SOI DRAM Low Power, Multi-Gigabit DRAM Cell Design Issues Using SOI Technology Fred Chen & Lixin Su May 12, 1999 A Presentation for EE241 Term Project Department of Electrical Engineering and Computer Sciences University of California at Berkeley

Fred Chen & Lixin Su SOI DRAM Outline of the Project Background Study –SOI Technology –Low Power DRAM Design DRAM Conceptual Design Using SOI –Spice3 for SOI Simulation –Simulations/Results/Conclusions Summary and Future Work

Fred Chen & Lixin Su SOI DRAM SOI Technology for DRAM Fully Depleted (FD) Partially Depleted (PD) Dynamically Depleted (DD) T box Substrate Body S ource Drain Depletion Gate VsVs VgVg VdVd T ox T si VbVb VpVp V bg

Fred Chen & Lixin Su SOI DRAM SOI Technology for DRAM Low Power Small channel leak for same drivability (1) Junction leak reduction (3) Charge/discharge current reduction (2) Body control current reduction (6) Related SOI Features (1) Small S-factor (4) Small substrate bias effect (2) Small Junction Cap. (5) Complete body isolation (3) Small Junction Area (6) Small Body Cap. Low Voltage High drive capability for same leak (1) Large cell readout signal (2) High speed operation (2) (4) Large high-data write margin (4) Easy to apply body control (5) Source: Shimomura et al., JSSC vol. 32, No. 11, Nov. 1997

Fred Chen & Lixin Su SOI DRAM SOI Technology for DRAM What Else? There’s more? : Reduced Second Order Effects –Radiation hardened: Almost Soft Error Free C s reduced  AREA reduced –Free from latchup Disadvantages: –Floating body effect –Self-heating effect Solution: –Body control through body contact schemes –Fully depleted SOI

Fred Chen & Lixin Su SOI DRAM Spice3 for SOI Simulation Source: UC Berkeley Device Group Versions: BSIMPD2.0 & BSIMPD2.0.1 & BSIMFD2.0 & BSIMDD2.0 BSIM3SOI1.3 Model Card: {PD,DD,FD} x {PMOS, NMOS} Spice3 Limitations: –Restricted.subckt & !.param => ! Sweep/Change MOS Parameter –!.measure => Extra Data Processing Need to Improve Work Efficiency!

Fred Chen & Lixin Su SOI DRAM Spice3 for SOI Simulation Simulation Flow: Perl Spice Deck Parameters Results Spice Model Card Script Switch PD DDFD Spice 3 Simulation Engine

Fred Chen & Lixin Su SOI DRAM Single Transistor SOI: The S-Factor

Fred Chen & Lixin Su SOI DRAM Single Transistor SOI: The S-Factor

Fred Chen & Lixin Su SOI DRAM Single Transistor SOI: The Kink

Fred Chen & Lixin Su SOI DRAM Single Transistor SOI: Pass Gate Leakage Current 0v 1.5v 0v ???

Fred Chen & Lixin Su SOI DRAM Low Power DRAM Design Typical large scale low power architectures –Multi-divided data lines –Shared sense amplifiers –Divided word lines Reduce C B, reduce C B ! Half-V dd pre-charge Boosted sense ground SOI

Fred Chen & Lixin Su SOI DRAM DRAM: Comparison Scheme Technology Comparison –Use identical architectures –Match relative performance of each technology model –Use single cell comparison (with SA) –Compare DRAM metrics for each technology

Fred Chen & Lixin Su SOI DRAM DRAM SOI: Cell & Sense Amplifier aa rr pp V dd /2 D Dbar W Wbar WrWr WL Cell Dummy Cell

Fred Chen & Lixin Su SOI DRAM DRAM SOI: Control Signals phip phia phir wr w wbar wl Write 0Read/RestoreWrite 1

Fred Chen & Lixin Su SOI DRAM DRAM SOI: Bit-Line Capacitance

Fred Chen & Lixin Su SOI DRAM Simulation Results

Fred Chen & Lixin Su SOI DRAM Round 1: Bulk vs. SOI

Fred Chen & Lixin Su SOI DRAM Round 2: PD vs. FD

Fred Chen & Lixin Su SOI DRAM Conclusions Performance: FDPD-ActBPD-FltBPD-FixB HighLow Power: FDPD-FixBPD-FltBPD-ActB LowHigh

Fred Chen & Lixin Su SOI DRAM PD vs. FD Tradeoffs Which to choose for DRAM? –Fully Depleted SOI Pros: Low Power, Low C J, low S-factor, no body contact needed, less sensitive to temperature variation Cons: Manufacturability, sensitivity to process variation –Partially Depleted (floating body) Pros: Easy to manufacture Cons: Floating body –Inside PD: body contact tradeoffs, see last slide

Fred Chen & Lixin Su SOI DRAM Work Done & Future Work Work Done: –Single transistor characterization for SOI –Comparison between bulk/different SOI body contact schemes for DRAM cell design Future Work: –More SOI simulation of each component of DRAM –More SOI simulation to study coupling effect, standby current, & pass gate leakage current –Voltage scaling & transistor sizing with SOI