UFO’07 26 June 2007 Siedlce 1 Use of Partial Orders for Analysis and Synthesis of Asynchronous Circuits Alex Yakovlev School of EECE University of Newcastle upon Tyne Collaboration with A. Semenov,W. Vogler, A. Kondratyev, V. Khomenko, M. Koutny, A. Madalinski, I. Poliakov

UFO’07 26 June 2007 Siedlce 2 Outline l Motivation l A bit of history l Circuit models in Petri nets l Properties to be checked l Problems with unfolding models l State Coding analysis l Visualisation using unfoldings l Deriving logic from unfoldings l What next?

UFO’07 26 June 2007 Siedlce 3 Motivation for asynchronous systems l Asynchronous (self-timed) systems help variability-tolerant design and optimize power-performance tradeoff for nanometer technology l Latest International Semiconductor Roadmap predicts 20% (40%) of designs will be asynchronous, and by 2012 (2020) l Active areas of asynchronous signalling and circuits: low power and low EMI processing (automotive, smart-card), networks on chip, GALS

UFO’07 26 June 2007 Siedlce 4 Motivation from circuit analysis l Self-timed circuits can be highly concurrent, e.g. use of pipeline data flow structures, use of parallel branches in control of CPUs, concurrent resource allocation schemes (multi-way arbiters, switches etc.) – state space can run into for 100s of signals. Hence analysis and verification using explicit state space traversal is hard

UFO’07 26 June 2007 Siedlce 5 Motivation from circuit synthesis l In the synthesis domain, resolving state encoding problems and constructing next- state functions using state space models is limited to signals (relatively small controllers) l Visualisation of state space is very hard, let alone examining groups of states about some properties

UFO’07 26 June 2007 Siedlce 6 Circuit specification

UFO’07 26 June 2007 Siedlce 7 State Graph

UFO’07 26 June 2007 Siedlce 8 Modified Specification

UFO’07 26 June 2007 Siedlce 9 The new State Graph…

UFO’07 26 June 2007 Siedlce 10 But how about this one?

UFO’07 26 June 2007 Siedlce 11 A bit of history Early examples: l Flow chart, change chart methods by Gilles, Swartwout and Shelly – late 50s, early 60s l Signal Graphs for handshake control structures by Jump and Thiagarajan – mid 70s l Circuit synthesis from Taxograms by Starodoubtsev – mid 80s l Circuit analysis and synthesis using Change Diagrams and their unfoldings by Kishinevsky, Kondtayev, Taubin and Varshavsky – late 80s. l Relation-based approach to analysis of STG models by Rosenblum and Yakovlev – late 80s

UFO’07 26 June 2007 Siedlce 12 A bit of history l Petri net unfolding prefix by McMillan (1992) l Unfolding prefix for STGs and circuits by Kondratyev et al. and Semenov (1995) l Unfolding-based analysis of Timed Circuits by Semenov and Yakovlev (1996) l Unfolding-based synthesis using cover approximations by Semenov et al. (1997) l Circuit analysis using contextual net unfoldings by Vogler et al. – (1998) l STG analysis using unfoldings and LP and SAT by Khomenko et al. ( ) l Circuit Synthesis from STG using unfoldings and SAT by Khomenko (2004) l Visualization of STG-based Synthesis by unfoldings by Madalinski et al. ( ) l Combining decomposition and unfolding for STG-based Synthesis by Khomenko and Shaefer (2007)

UFO’07 26 June 2007 Siedlce 13 Circuit models in Petri nets l Event-based models: Petri net transitions represent signal events l Level-based models: Petri net places model the values of signals

UFO’07 26 June 2007 Siedlce 14 Logic Circuit Modelling Event-driven elements Petri net equivalents C Muller C- element Toggle

UFO’07 26 June 2007 Siedlce 15 Logic Circuit Modelling Level-driven elements Petri net equivalents NAND gate x(=1) y(=1) z(=0) NOT gate x(=1) y(=0) x=0 x=1 y=0 y=1 b x=0 x=1 z=0 z=1 y=0 y=1 Read arcs

UFO’07 26 June 2007 Siedlce 16 Circuit Petri Nets Level-driven elements Petri net equivalents NAND gate x(=1) y(=1) z(=0) NOT gate x(=1) y(=0) x=0 x=1 y=0 y=1 b x=0 x=1 z=0 z=1 y=0 y=1 Self-loops in ordinary P/T nets

UFO’07 26 June 2007 Siedlce 17 Logic Circuit Modelling: examples Pipeline data Stage Data In Data Out Pipeline control Stage Rin Ain Rout Aout Data Enable Pipeline control must guarantee: Handshake protocols between the stages Safe propagation of the previous datum before the next one

UFO’07 26 June 2007 Siedlce 18 Event-driven circuit Non-speed- independence can be detected via non-1-safeness check

UFO’07 26 June 2007 Siedlce 19 Level-driven circuit

UFO’07 26 June 2007 Siedlce 20 Level-driven circuit Set-part

UFO’07 26 June 2007 Siedlce 21 Level-driven circuit Reset-part

UFO’07 26 June 2007 Siedlce 22 Level-driven circuit Without y2 in Set part of y1 this trace can happen: I2+ C1+ I2- C2+ I1+ C1- I2+ C2- C1+ This sort of structures (acyclic Change Diagrams) were built directly from logic eqn’s by Kishinevsky et al. – but only for distributive circuits

UFO’07 26 June 2007 Siedlce 23 Level-driven circuit Without y2 in Set part of y1 this trace can happen: I2+ C1+ I2- C2+ I1+ C1- I2+ C2- disabling C1+

UFO’07 26 June 2007 Siedlce 24 Properties analysed l Functional correctness (need to model environment) l Deadlocks l Hazards: –non-1-safeness for event-based –non-persistency for level-based l Timing constraints –Absolute (need Timed Petri nets) –Relative (compose with a PN model of order conditions)

UFO’07 26 June 2007 Siedlce 25 Circuit Petri Nets Level-driven elements Petri net equivalents NAND gate x(=1) y(=1) z(=0) NOT gate x(=1) y(=0) x=0 x=1 y=0 y=1 b x=0 x=1 z=0 z=1 y=0 y=1 Self-loops in ordinary P/T nets

UFO’07 26 June 2007 Siedlce 26 Unfolding Nets with Read Arcs PN with self- loops Unfolding with self-loops Combinatorial explosion due to splitting the self-loops Unfolding with read arcs (work with W. Vogler, CONCUR 1998) Works nicely for read- persistent nets only

UFO’07 26 June 2007 Siedlce 27 Petri Net mapping: an example source gate-level model corresponding Petri Net Multiple read arcs exiting one place: bad for unfolding! Only one read arc per place: minimal impact on unfolding

UFO’07 26 June 2007 Siedlce 28 Unfolding and read arcs: statistics Test case Net size (places/ transitions) Without place splittingWith place splitting N of events Unfolding time N of events Unfolding time Counterflow stage controller 24/ ms82125 ms SDFS ARISC90/90>50000>1 min (halted) ms SDFS fork/join112/132>50000>1 min (halted) ms SDFS fork/join early prop. 112/134>50000>1 min (halted) ms

UFO’07 26 June 2007 Siedlce 29 STG Unfolding l Unfolding an interpreted Petri net, such as a Signal Transition Graph, requires keeping track of the interpretation – each transition is a change of state of a signal, hence each marking is associated with a binary state l The prefix of an STG must not only “cover” the STG in the Petri net (reachable markings) sense but must also be complete for analysing the implementability of the STG, namely: consistency, output-persistency and Complete State Coding

UFO’07 26 June 2007 Siedlce 30 STG Unfolding a+ b+ c+ d+ d- p1 p2 p3 p4 p5 p1 p2 p3 p4 p5 STG Uninterpreted PN Reachability Graph Binary-coded STG Reach. Graph (State Graph) p1(0000) abcd p2(1000) a+ p3(0100) b+ c+ p4(1010) p4(0110) p5(1011) d+ p5(0111) a+ b+ c+ p1 p2 p3 d+ d- p4 p5 STG unfold. prefix d+ d- p4 p5

UFO’07 26 June 2007 Siedlce 31 STG Unfolding a+ b+ c+ d+ d- p1 p2 p3 p4 p5 p1 p2 p3 p4 p5 STG Uninterpreted PN Reachability Graph Binary-coded STG Reach. Graph (State Graph) p1(0000) abcd p2(1000) a+ p3(0100) b+ c+ p4(1010) p4(0110) p5(1011) d+ p5(0111) a+ b+ c+ p1 p2 p3 d+ d- p4 p5 STG unfold. prefix Not like that!

UFO’07 26 June 2007 Siedlce 32 Consistency and Signal Deadlock p1 a+ a- b- b+ b- p3 p2 p4 p5 p6 p2p4 p1p4 p2p5 p1p5 p3p4 p3p5 a- a+ b+ b- p1p6 p2p6 p3p6 a+ b+ b- STG PN Reach. Graph STG State Graph p1p6(00) p2p6(10) p3p6(01) a+ b+ b- ab a- p1p4(00) a+ p2p4(10) b+ p2p5(11) b- p3p4(01) b+ p1p5(01) b- Signal deadlock wrt b+ (coding consistency violation)

UFO’07 26 June 2007 Siedlce 33 Signal Deadlock and Autoconcurrency p1 a+ a- b- b+ b- p3 p2 p4 p5 p6 STG STG State Graph p1p6(00) p2p6(10) p3p6(01) a+ b+ b- ab a- p1p4(00) a+ p2p4(10) b+ p2p5(11) b- p3p4(01) b+ p1p5(01) b- Signal deadlock wrt b+ (coding consistency violation) STG Prefix p1 a+ a- b+ b- b+ p3 p2 p4 p5 p6 a+ p1 b- p2 b- Autoconcurrency wrt b+

UFO’07 26 June 2007 Siedlce 34 Verifying STG implementability l Consistency – by detecting signal deadlock via autoconcurrency between transitions labelled with the same signal (a* || a*, where a* is a+ or a-) l Output persistency – by detecting conflict relation between output signal transition a* and another signal transition b* l Complete State Coding is less trivial – requires special theory of binary covers on unfolding segments

UFO’07 26 June 2007 Siedlce 35 Example: VME Bus Controller lds-d-ldtack-ldtack+ dsr-dtack+d+ dtack-dsr+lds+ Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dtack

UFO’07 26 June 2007 Siedlce 36 Example: Encoding Conflict dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d M’’M’

UFO’07 26 June 2007 Siedlce 37 Example: Encoding Conflict lds- d- ldtack- ldtack+ dsr- dtack+ d+ dtack- dsr+lds+ dsr+ e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 Code(conf’)=10110 Code(conf’’)=10110

UFO’07 26 June 2007 Siedlce 38 Detection of encoding conflicts using SAT solvers l A special case of model checking! l  has the form CONF 1  CONF 2  VIOL l VIOL is a constraint stating that the two configurations have the same final encodings and enable different sets of output signals

UFO’07 26 June 2007 Siedlce 39 Beyond model checking Problem: model checking just tells you whether some property holds, but it’s not enough for resolution of encoding conflicts and for deriving equations!

UFO’07 26 June 2007 Siedlce 40 Example: Resolving the conflict dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d csc+ csc M’’M’

UFO’07 26 June 2007 Siedlce 41 Example: Encoding Conflict lds- d- ldtack- ldtack+ dsr- dtack+ d+ dtack- dsr+lds+ dsr+ e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 Code(conf’)=10110 Code(conf’’)=10110 core

UFO’07 26 June 2007 Siedlce 42 Example: Resolving the conflict lds-d-ldtack-ldtack+ dsr-dtack+d+ dtack-dsr+lds+ csc+ csc-

UFO’07 26 June 2007 Siedlce 43 Visualising conflicts: Height map l Cores often overlap l Highest ‘peaks’ are good candidates for signal insertion l Analogy with topographic maps Core 1 Core 2 A1 A2 A3 Core 3

UFO’07 26 June 2007 Siedlce 44 Height map: an example Highest peak Core mapHeight map csc+

UFO’07 26 June 2007 Siedlce 45 Logic synthesis: Next-state function l The next-state function of each output or internal signal will be implemented as a logic gate in the circuit l Defined for each such signal z at each reachable state M as Nxt z (M) = Code z (M)  Enabled z (M) l The value is undefined (‘don’t care’) for unreachable states

UFO’07 26 June 2007 Siedlce 46 Example: Deriving equations dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d csc+ csc

UFO’07 26 June 2007 Siedlce 47 Example: Deriving Equations CodeNxt dtack Nxt lds Nxt d Nxt csc Eqnd d  csccsc  ldtack dsr  (  ldtack  csc)

UFO’07 26 June 2007 Siedlce 48 Example: Resulting Circuit Device d Data Transceiver Bus dsr dtack lds ldtack csc

UFO’07 26 June 2007 Siedlce 49 Logic synthesis on unfoldings Challenge: how to do this without building the state graph, and using only the unfolding prefix?

UFO’07 26 June 2007 Siedlce 50 Logic synthesis on unfoldings Need to know how to compute projections! l Problem: given a prefix and a set X of signals which are known to be a support of the given output or internal signal z, compute the truth table of Nxt z l Let  = CONF  CODE X where CODE X relates the values of all signals in X with the configuration l Compute the projection of  onto X

UFO’07 26 June 2007 Siedlce 51 Example: computing projections a b c d e Proj {a,b,c}  abc a  b  =(a  b)(  a   b)(c  d  e)

UFO’07 26 June 2007 Siedlce 52 Computing projections Proj {a,b,c}  abcde UNSAT (a  b  c) a  b  =(a  b)(a  b)(c  d  e) Incremental SAT

UFO’07 26 June 2007 Siedlce 53 Further developments l Unfoldings for PNs with read arcs, beyond read-persistent nets l Unfoldings for large circuit models (higher levels) l Unfoldings of circuits with timing constraints l Unfoldings for synthesis and re-synthesis driven by verification and optimization

UFO’07 26 June 2007 Siedlce 54 Circuit Petri nets The meaning of these numerous self-loop arcs is however different from self-loops (which take a token and put it back) These should be test or read arcs (without consuming a token) From the viewpoint of analysis we can disregard this semantic discrepancy (it does not affect reachability graph properties!) and use ordinary PN unfolding prefix for analysis, BUT …

UFO’07 26 June 2007 Siedlce 55 Experimental results (from Semenov) Example with inconsistent STG: PUNT quickly detects a signal deadlock “on the fly” while Versify builds the state space and then detects inconsistent state coding

UFO’07 26 June 2007 Siedlce 56 General-purpose Petri Net mapping technique Signals are represented as elementary cycles Positive (negative) transitions of the cycles are built according to set (reset) logical function The logical functions are converted into DNF form and undergo boolean minimisation For each clause of the minimised DNF, a transition is added Transitions are connected to places corresponding to the literals of the DNF clause by means of read arcs read arcs