Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s VHDL course webpage

2Kazi Fall 2006 EEGN 494 Arrays Arrays are collection of objects of the same type. They can be one-dimensional (1D), two- dimensional (2D), or one-dimensional-by- one-dimensional (1Dx1D) Scalar1D1D x 1D D data arays

3Kazi Fall 2006 EEGN 494 Arrays Scalars: BIT, STD_LOGIC, STD_ULOGIC and BOOLEAN Vectors: BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR, INTEGER, SIGNED, and UNSIGNED There are no pre-defined 2D or 1D x 1D arrays Hence need to be specified by the user To do so, a TYPE must be first defined, then the new SIGNAL, VARIABLE or CONSTANT can be declared using that data type.

4Kazi Fall 2006 EEGN 494 Arrays: Syntax of defining an array To specify a new array type: TYPE type_name IS ARRAY (specificaiton) of data_type; To make use of the new array type: SIGNAL signal_name: type_name [:= initial value]; Example: TYPE row IS ARRAY (7 downto 0) OF STD_LOGIC; -- 1D array TYPE matrix IS ARRAY (0 to 3) of row; -- 1Dx1D array SIGNAL x: matrix -- 1Dx1D signal

5Kazi Fall 2006 EEGN 494 Arrays: Syntax of defining an array Another way of constructing the 1Dx1D array TYPE matrix IS ARRAY (0 to 4) of STD_LOGIC_VECTOR (7 DOWNTO 0) Example: 2D array The array below is truly two-dimensional. Notice that its construction is not based on vectors, but rather entirely on scalars TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) of STD_LOGIC; --2D array

6Kazi Fall 2006 EEGN 494 ROM (Read Only Memory) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rom is GENERIC ( bits: INTEGER := 8 -- # of bits per word words: INTEGER := 8 ); -- # of words in the memory PORT ( addr : IN INTEGER RANGE 0 to words - 1; data : OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0)); END rom; ARCHITECTURE rom of rom IS TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0); CONSTANT memory: vector_array := ( " ", " ", " ", " ", " ", " ", " ", " ", " ",); BEGIN data <= memory(addr); END rom;

7Kazi Fall 2006 EEGN 494 RAM (Random Access Memory) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram is GENERIC ( bits: INTEGER := 8 -- # of bits per word words: INTEGER := 8 ); -- # of words in the memory PORT ( wr_ena: IN STD_LOGIC; -- write enable clk: IN STD_LOGIC; -- clock addr: IN INTEGER RANGE 0 to words -1; data_in:: IN STD_LOGIC_VECTOR (bits - 1 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)); END ram ARCHITECTURE ram of ram IS TYPE vector_array is ARRAY (0 to words -1) of STD_LOGIC_VECTOR (bits-1 DOWNTO 0); signal memory: vector_array; BEGIN PROCESS (clk, wr_ena) BEGIN IF (wr_ena = '1') THEN IF (clk'EVENT AND clk = '1') THEN memory(addr) <= data_in; END IF; END PROCESS; data_out <= memory(addr); END ram;

8Kazi Fall 2006 EEGN 494 CASE: conditional statements CASE is another statement intended exclusively for sequential code (along with IF, LOOP, and WAIT) CASE identifier IS WHEN value => assignments; …….. END CASE; CASE control IS WHEN “00” => x <= a; y <= b; WHEN “01” => x <= b; y <= a; WHEN OTHERS => x <= “0000”; y <= “zzzz”; END CASE;

9Kazi Fall 2006 EEGN 494 RANGE RANGE <> is used to indicate that the range is unconstrainded INTEGER range is to NATURAL RANGE <>, on the other hand, indicates that the only restriction is that the range must fall within the NATRUAL RANGE Natural range is 0 to

10Kazi Fall 2006 EEGN 494 CASE: Two-digit Counter with Seven Segment Display

11Kazi Fall 2006 EEGN 494 CASE: Two-digit Counter with Seven Segment Display LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY counter IS PORT (clk, reset: std_logic; digit1, digit1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END counter; ARCHITECTURE counter of counter IS BEGIN PROCESS (clk, reset) VARIABLE temp1: INTEGER RANGE 0 TO 10; VARIABLE temp2: INTEGER RANGE 0 TO 10; Begin IF (reset = '1') THEN temp1 := 0; temp2 := 0; ELSIF (clk'event and clk = '1') THEN temp1 := temp1 + 1; IF (temp1 = 10) THEN temp1 := 0; temp2 := temp2 + 1; IF (temp2 := 10) THEN temp2 := 0; END IF; CASE temp1 IS WHEN 0 => digit1 <= " ";--7E WHEN 1 => digit1 <= " ";--30 WHEN 2 => digit1 <= " ";--6D WHEN 3 => digit1 <= " ";--79 WHEN 4 => digit1 <= " ";--33 WHEN 5 => digit1 <= " ";--5B WHEN 6 => digit1 <= " ";--5F WHEN 7 => digit1 <= " ";--70 WHEN 8 => digit1 <= " ";--7F WHEN 9 => digit1 <= " B WHEN OTHERS => NULL; END CASE; CASE temp2 IS WHEN 0 => digit2 <= " ";--7E WHEN 1 => digit2 <= " ";--30 WHEN 2 => digit2 <= " ";--6D WHEN 3 => digit2 <= " ";--79 WHEN 4 => digit2 <= " ";--33 WHEN 5 => digit2 <= " ";--5B WHEN 6 => digit2 <= " ";--5F WHEN 7 => digit2 <= " ";--70 WHEN 8 => digit2 <= " ";--7F WHEN 9 => digit2 <= " B WHEN OTHERS => NULL; END CASE; END PROCESS; END COUNTER;

12Kazi Fall 2006 EEGN 494 As the name says, LOOP is useful when a piece of code must be instantiated several times. There are several ways of using LOOP FOR/LOOP: The loop is repeated for a fixed number of times [label:] FOR identifier IN range LOOP (sequential statements) END LOOP [label]; FOR i IN 0 TO 5 LOOP x(i) <= enable AND w(i+2); y(i) <= w(i); END LOOP MyLoop; In the code the love will be repeated unconditionally until it reaches 5 (i.e. six times) LOOP

13Kazi Fall 2006 EEGN 494 WHILE/LOOP: The loop is repeated until a conditon no longer holds [label:] WHILE condition LOOP (sequential statements) END LOOP [label]; WHILE (I < 10) LOOP WAIT UNTIL clk’EVENT and clk = ‘1’; (other statements) END LOOP; In the code the love will be repeated as long as i < 10 condition holds. LOOP

14Kazi Fall 2006 EEGN 494 EXIT: Used for ending the loop [label:] EXIT [label] [WHEN condition]; FOR i IN data’RANGE LOOP CASE data(i) IS WHEN ‘0’ => count := count + 1; WHEN OTHERS => EXIT; END CASE; END LOOP; LOOP

15Kazi Fall 2006 EEGN 494 NEXT: Used for skipping loop steps [label:] NEXT [label] [WHEN condition]; FOR I IN 0 TO 15 LOOP NEXT WHEN i = 10; (……..) END LOOP; In this example, NEXT causes LOOP to skip one iteration when i = 10 LOOP

16Kazi Fall 2006 EEGN 494 The design counts the number of leading 0s in a binary vector, starting from the left end. This solutions shows the usage of LOOP/EXIT. In this example, the loop will end as soon as a ‘1’ is found in the data vector. Therefore, it is appropriate for counting the number of zeros that precede the first one. LOOP: Example: Leading Zeros

17Kazi Fall 2006 EEGN 494 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY LeadignZeros IS PORT (data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); zeros : OUT INTEGER RANGE 0 TO 8 ); END LeadingZeros; ARCHITECTURE behavior of LeadingZeros IS BEGIN PROCESS (data VARIABLE count: INTEGER RANGE 0 TO 8; BEGIN count := 0; FOR i IN data'RANGE LOOP CASE data(i) IS WHEN '0' => count := count + 1; WHEN others => EXIT; END CASE; END LOOP; zeros <= count; END PROCESS; END behavior; Simulation results should be: With data = “ ” (decimal 0), 8 zeros are detected; when data = “ ”, seven zeros are encountered LOOP: Example: Leading Zeros

18Kazi Fall 2006 EEGN 494 Assignment: Write test benches for the ROM and RAM (slides 6 & 7) For the ROM the testbench should read all the memory locations as listed in the lecture code Modify the constants in the ROM and read the all the locations RAM: Write arbitrary data in RAM and read it back Modify the code to make the RAM bigger. It should have 255 addresses Modify the testbench such that all data in written into the RAM locations Testbench should read the stored data to ensure that the written data is the same as the read data. Write a report that explains what you did Due date October 26

19Kazi Fall 2006 EEGN 494 PROJECT TALK Let us discuss Final projects Moving forward we will be using Mentor Graphics Leonardo for Synthesis of RTL code into gates.