May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 1 Use of Hierarchy in Fault Collapsing Raja K. K. R. Sandireddy Intel Corporation Hillsboro, OR 97124, USA Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 2 Outline Introduction –Main idea –Background on fault collapsing Hierarchical fault collapsing –Method –Advantages: Smaller collapse ratio Reduced CPU time Results Conclusions

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 3 The General Idea of Hierarchy Circuit (top level In hierarchy) Subnetwork analyzed once, placed in library. interconnects Lowest-level block (gates and interconnects), analyzed in detail, saved in library. Analysis at n th level:1. Copy preprocessed internal detail of n-1 level from library. 2. Process n th level interconnects.

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 4 Background on Fault Collapsing DUT Generate fault list Collapse fault list Generate test vectors Fault model Required fault coverage Test Vector Generation Flow

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 5 Structural Fault Collapsing Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set. –Equivalence collapsed set = {a 0, b 0, c 0, c 1 } –Collapse ratio = 4/6 = 0.67 Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults. – Dominance collapsed set = {a 0, b 0, c 1 } –Collapse ratio = 3/6 = 0.5 Total faults = 6

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 6 Functional Collapsing: XOR Cell a b c d e g h i j k m c 0 c 1 d0d1d0d1 Functional dominance examples: d 0 → j 0, k 1 → g 0 f All faults = 24 Str. Equ. Faults = 16 Str. Dom. Faults = 13 Func. Dom. Faults = 4

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 7 Hierarchical Fault Collapsing Create a library –For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done. –For larger circuits, use structural collapsing. For hierarchical circuits, at any level of hierarchy, say n th level: –Read-in preprocessed (library) collapse data of (n-1) level sub-circuits. –Structurally collapse the interconnects and gate faults of n th level. References: -R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014– R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 8 Results: Collapse Ratio Advantage Collapse ratio Total faults603,71459,3941,1162,646 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder) are functionally collapsed. Programs used:1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 9 Fault Collapsing Time for Flattened Circuits CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory.

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 10 Analysis of CPU Time (s) for Flattened Circuits

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 11 Analysis of CPU Time (s) for Hierarchical Circuits bit bit bit bit bit bit bit bit TotalLibrary Equiv.+Dom. Collapsing Structure Processing

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 12 Comparison of CPU Times for Hierarchical and Flattened Circuits

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 13 CPU Time (s) Improvement by Hierarchy Hierarchical circuitFlattened circuit bit bit bit bit bit bit bit bit Multi-levelTwo-levelOur ProgramHitec

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 14 CPU time (s) for Hierarchical Collapsing

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 15 Rent’s rule Rent’s Rule: Number of inputs and outputs terminals (T) for a typical block containing G logic gates is given by: T = K × G ~ 0.5 to 0.65 For ripple carry adders,~ 1. CPU time for collapsing is proportional to G 2.  G is proportional to area

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 16 Hierarchical Multipliers n/2×n/2 Additional Circuitry n × n multiplier ~ √G inputs ~ √G outputs n/2×n/2 Here ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size.

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 17 Conclusions For larger circuits described hierarchically, use hierarchical fault collapsing. Hierarchical fault collapsing: –Better (lower) collapse ratios due to functional collapsed library –Order of magnitude reduction in collapse time. Smaller fault sets: –Fewer test vectors –Reduced fault simulation effort –Easier fault diagnosis. Dom. Collapsed Set Size (Collapse Ratio) CPU s FlatHierarchicalFlatHier (0.48)98304 (0.21) bit Adder

May 13, 2005Sandireddy & Agrawal: Hierarchy in Fault Collapsing 18 THANK YOU