Jan. 6, 2006VLSI Design '061 On the Size and Generation of Minimal N-Detection Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.

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Jan. 6, 2006VLSI Design '061 On the Size and Generation of Minimal N-Detection Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL USA 19 th International Conference on VLSI Design, Hyderabad, January 3-7, 2006

Jan. 6, 2006VLSI Design '062 Motivation for This Work N-detection vectors are known to have a higher coverage of “real defects”. Increased test length for N-detection tests directly impacts testing cost. Efficient ways to find minimal N-detection test set are still evolving. There is no proven lower bound on the size of the N-detection vectors.

Jan. 6, 2006VLSI Design '063 Outline Introduction Theoretical minimum for an N-detection test set ILP based N-detection approach Results Conclusions

Jan. 6, 2006VLSI Design '064 Minimal Single-Detection Tests Independence graph: Nodes are faults and edges represent pair- wise independence relationships. Example: c17 [1]. An Independent Fault Set (IFS) is a maximal clique in the graph. Size of IFS is a lower bound on test set size (Akers et al., ITC-87) So, the minimal test set for these 11 faults is ‘4’. [1] A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9th VLSI Design and Test Symp., Aug. 2005, pp

Jan. 6, 2006VLSI Design '065 Theoretical Minimum of an N-Detection Test Set Theorem 1: The size of the largest clique in the independence graph is a lower bound on single detection test set size [Akers et al. ITC-87]. Theorem 2: A lower bound on the size of the N-detection test set is N times the size of the largest clique in the independence graph. 1 N test Vecs So, at least 4N vectors are needed to detect each fault ‘N’ times.

Jan. 6, 2006VLSI Design '066 4-Bit ALU: N-Detection Vectors

Jan. 6, 2006VLSI Design '067 ILP Based N-Detection Approach Use any ATPG to obtain a set of k vectors that detects every fault at least M times, where M  N. Use Diagnostic fault simulation to get the vector subset T j for each fault j. Assign integer variable t i to i th vector such that, t i =1 if i th vector included in the minimal set t i =0 if i th vector not included

Jan. 6, 2006VLSI Design '068 Objective and Constraints of ILP Objective: Constraints: N j is the multiplicity of detection for the j th fault. N j can be selected for individual faults based on some criticality criteria or on the capability of the initial vector set. Theorem 3: When the minimization is performed over an exhaustive set of vectors, an ILP solution that satisfies the above expressions is a minimum N-detection test set.

Jan. 6, 2006VLSI Design '069 Minimal 3-Detection Test Set for c17 ATALANTA generates 4 test sets (M = 4); repeated vectors are removed. HOPE is used to perform diagnostic fault simulation on the vector set. Simulation information is used to create constraints for the ILP. sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x sa1 x X sa0 X sa0 X sa0 X sa0 X sa0 sa1 x sa1 x

Jan. 6, 2006VLSI Design '0610 Constraint Generation Fault 1 is detected by the vectors 1, 2, 15, 16, 22, 24. Fault 2 is detected by the vectors 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 22, 24, 28, so on.... Now the Objective is: and the constraints are: Constraint_ ‘F1’ : t 1 +t 2 +t 15 +t 16 +t 22 +t 24 ≥ 3 Constraint_ ‘F21’ : t 13 +t 15 +t 16 +t 19 +t 23 +t 24 ≥ 3

Jan. 6, 2006VLSI Design '0611 Minimum Test Sets from ILP The minimum 3-detect test set size is 13 (lower bound = 12). Vectors are: 2, 6, 7, 11, 14, 15, 16, 17, 18, 21, 23, 24, 28. Suppose fault ‘21’ is a critical fault to be detected 5 times: Constraint_‘F21’: t 13 +t 15 +t 16 +t 19 +t 23 +t 24 The minimum test set given by ILP has 14 vectors. Vectors are: 2, 6, 7, 11, 12, 13, 14, 15, 16, 17, 18, 19, 23, 28. For large circuits the change in test size is negligible.

Jan. 6, 2006VLSI Design ' Detection Tests for Benchmarks Hamzaoglu and Patel, IEEE-TCAD, Aug Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002

Jan. 6, 2006VLSI Design '0613 CPU Time for 15-Detection Tests Ultra-5, * Ultra-10, ** Sun Fire 280R Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002

Jan. 6, 2006VLSI Design '0614 Classifying Combinational Circuits TYPE - I: TYPE – II: c499, c1355, c1908 c880, c2670, c7552 Output cones have large overlap. Any vector detecting a fault F2 will have high probability of detecting other faults, say fault F3 or F1. Non-overlapping output cones. Any vector detecting a particular fault, will have very less probability of detecting any other fault.

Jan. 6, 2006VLSI Design '0615 Example: Ripple Carry Adders 1-b a b c_in s_out c_out

Jan. 6, 2006VLSI Design '0616 Conclusion The theoretical lower bound on the N-detection tests is useful in assessing the minimality of such tests. ILP is an effective method for minimizing tests, though further improvement is possible. The formulation of ILP allows custom selection of multiplicity of detection for individual faults. Contributions of this work: –Theoretical lower bound on N-detection tests. –ILP method for deriving minimal N-detection tests.

Jan. 6, 2006VLSI Design '0617 Thank You...