DØ Collaboration Meeting October 10, DØ RunIIb Trigger Upgrade Vivian O’Dell, FNAL for the DØ Trigger Upgrade Group

DØ Collaboration Meeting October 10, Run IIb Trigger Upgrades  Strategy and Motivation u Latest Luminosity Predictions u Basic trigger upgrade strategy  Technical progress  Installation/Commissioning plans  Summary

DØ Collaboration Meeting October 10, Run IIb Luminosity Projections ~1.6e32 ~2.8e32 Accelerator draft plan: Peak luminosities Peak Luminosity (x10 30 cm -2 sec -1 ) You are here Peak FY03 ~4.5e31

DØ Collaboration Meeting October 10, Core Trigger Menu Simulations Total L1 bandwidth budget= ~3 kHz Total rate: ~15kHz ~30kHz ~3.2kHz Additional headroom available from topological cuts available in upgraded L1cal Higher mu p T threshold with upgraded CTT 1E32 2E32 2E32

DØ Collaboration Meeting October 10, Ingredients of the Trigger Upgrade  Level 1 u Calorimeter trigger upgrade s sharpens turn-on trigger thresholds s more topological cuts u Calorimeter track-match s fake EM rejection s tau trigger u L1 Tracking trigger upgrade s improved tracking rejection esp. at higher occupancies s inputs to Calorimeter track-mathc  Level 2 u L2 Processor upgrades for more complex algorithms u Silicon Track Trigger expansion s More processing power s use trigger inputs from new silicon layer 0  Upgrade/maintain DAQ/Online systems

DØ Collaboration Meeting October 10, The L1Cal Team SaclayADFs/ADF Timing/Splitters u Physicists: J.Bystricky, P.LeDu*, E.Perez u Engineers:D.Calvet, Saclay Staff Columbia/NevisTABs/GABs/VME-SCL u Physicists:H.Evans*, J.Parsons, J.Mitrevski u Engineers:J.Ban, B.Sippach, Nevis Staff Michigan StateFramework/Online Software u Physicists:M.Abolins* u Engineers:D.Edmunds, P.Laurens NortheasternOnline Software u Physicists:D.Wood FermilabTest Waveform Generator u Engineers:G.Cancelo, V.Pavlicek, S.Rapisarda * L1Cal Project Leaders

DØ Collaboration Meeting October 10, Run IIa Limitations  Poor Et-res. (Jet,EM,MEt) u slow turn-on curves s 5 Gev TT thresh  80% eff. for 40 GeV jets u low thresholds  unacceptable rates at L = 2  (L = 2e32) ZH  vvbbJet Trigger 2 TT>5 GeV + MEt>10 GeV 1.3W  evEM Trigger 1 TT>10 GeV Rate (kHz)Phys. ChanTrigger L1 Rate Limit <5 kHz

DØ Collaboration Meeting October 10, Run IIb Solutions (2)  Solution for Rates: Sliding Windows Algorithm u Et cluster local max. search on 40  32 (  ) TT grid u Jet, EM & Tau algo’s u Better calc of missing Et u Topological Triggers u Jet, EM clust output for matching with L1 Tracks  Benefits u  2.5–3 Jet Rate reduction at constant efficiency s ZH  vvbb Rate: 2.1  0.8 kHz u Similar gains for EM & Tau u MEt, Topological Triggers under study Jet Algo EM AlgoTau Algo

DØ Collaboration Meeting October 10, Technical progress: L1Cal ADC+digital filtering Clustering Global sums & topological

DØ Collaboration Meeting October 10, Signal Splitter  Access to Real TT Data using “Splitter” Boards u designed/built by Saclay u active split of analog signals at CTFE input u 4 TTs per board u installed: Jan  Splitter Data u no perturbation of Run IIa L1Cal signals u allows tests of digital filter algorithm with real data

DØ Collaboration Meeting October 10, ~1300 components on both sides of a 14-layer class 6 PCB VME interface & glue logic Channel Link Serializers Core FPGA logic DC/DC converters Analog Section and ADCs VMEDigital OutAnalog In ADF Prototype

DØ Collaboration Meeting October 10, TAB Prototype power Channel Link Receivers (x30) Sliding Windows Chips (x10) L2/L3 Output (optical) VME/SCL Output to GAB Output to Cal-Track (x3) ADF Inputs (x30) Global Chip Internal Functions ~Fully Tested

DØ Collaboration Meeting October 10, VME/SCL Board  New Comp. of TAB/GAB system u proposed:Feb 03 u change control:Mar 03  Interfaces to u VME (custom protocol) s not enough space on TAB for standard VME u D0 Trigger Timing (SCL) u (previously part of GAB)  Why Split off from GAB u simplifies system design & maintenance u allows speedy testing of prototype TAB  Prototype at Nevis: May 12 u main VME & SCL functionality tested & working serial out x9 (VME & SCL) VME interface SCL interface local osc’s & f’out (standalone runs) Fully Tested

DØ Collaboration Meeting October 10, TAB/GAB Test Card TAB/GAB Data Rates u TAB: LVDS 424 MHz s (channel link) u GAB: LVDS 636 MHz s (stratix) Test Card at Nevis u Start Designmid-Aug u Board at Nevis29-Sep u Cost~$2K  Status u ADF-to-TAB xmit tested before integration u Will test TAB-to-GAB before sending out GAB for fabrication Channel Link TAB (ADF sim) power VME / SCL Cyclone Stratix S10 LVDS xmit/rcvr TAB (GAB in sim) Loopback

DØ Collaboration Meeting October 10, Prototype Integration Tests  Want to start “System Tests” asap u need to check cross-group links early  First Tests with Prototypes starting now u SCL  VME/SCL  TAB, ADF u BLS Data (split)  ADF  TAB u Flexible, staged schedule allows components to be included as they become available  Set up semi-permanent Test Area (thanks to J. Anderson’s group at FNAL) u outside of Movable Counting House u connection to SCL, split data signals u allows L1Cal tests without disturbing Run IIa data taking

DØ Collaboration Meeting October 10, Technical progress: L1Cal-Track Trigger  University of Arizona u J. Steinberg u D. Tompkins u C. Leeman u N. Wallace u B. Gmyrek u K. Johns u E. Varnes  Exploit new L1Cal trigger  Improve Run IIa  matching granularity x8  Needed in triggers for Higgs searches  electrons in WH and H  W * W modes  taus in H   and H +    Fake EM rejection is improved by ~x2  Fake  rejection is improved by ~x10

DØ Collaboration Meeting October 10, Hardware Progress  Block diagram of new Univeral Flavor Board: only really new board needed for L1 cal- track Flavor board (daughter) MTCxx (mother)

DØ Collaboration Meeting October 10, L1CalTrack Status  MTCxx (Trigger Cards) u Preproduction design complete u Layout and final checks in progress u Goal is to submit in November 03  UFB (Flavor Board) u Prototypes in hand u Boundary scan and downloading OK u Receiver/transmitter testing in progress u L1MU “05” algorithm implemented in Stratix EP1S20F780C7 (simulated but not tested) u H   algorithm implementation in progress  MTCM (Crate Manger) u Not started, but only minimal changes to the existing design

DØ Collaboration Meeting October 10, L1CalTrack Status  Infrastructure u VME crates, processors, power supplies, cables in hand u L1CTT to L1CalTrack cables being installed this weekend (not terminated) u Rack space in MCH1 identified (but not settled)  Commissioning u Plan is to use spare L1MU cards in L1CalTrack crates to establish communication with TF and L3 u Replace spares with L1CalTrack cards as available  Simulator u Work has started writing the L1CalTrack package and integrating it into the D0 Trigger Simulator

DØ Collaboration Meeting October 10, L1CTT Upgrade  Boston Univ u M. Narain u G. Redner u S. Wu  Fermilab u M. Johnson u J. Olson u F. Borcherding  Notre Dame u M. Hildreth  Manchester u L. Han u T. Wyatt  Kansas u G. Wilson  Brown u R. Partridge  Indiana u K. Stevenson

DØ Collaboration Meeting October 10, Technical Progress: L1Central Tracking Trigger  Tracking trigger rates sensitive to occupancy  Upgrade stategy: u Narrow tracker roads by using individual fiber hits (singlets) rather than pairing adjacent fibers (doublets) u Cal-track matching

DØ Collaboration Meeting October 10, L1 CTT Implementation  Digital Front End Axial (DFEA) daughter cards get replaced with new layout with larger FPGA’s (Xilinx Virtex-II XC2V6000) u Only 80 daughter cards get replaced; u rest of Run IIa system remains intact  Baseline algorithms compiled; occupy ~40% of the resources of the XC2V6000’s. DFEA layout with new FPGA footprints

DØ Collaboration Meeting October 10, Run IIb L1CTT Progress  Implemented prototype firmware (Boston U) u Includes equation files from all 4 momentum bins s p T >10 GeV, 5<p T <10 GeV, 3<p T <5 GeV, 1.5<p T <3 GeV  Resources used: u DFEA logic is implemented in two FPGAs Prototype DFEA: 10/17/03 prototype PCB returned 10/31/03 first prototype assembled. 11/30/03 prototype fully tested

DØ Collaboration Meeting October 10, L2  eta Upgrade 6U board Compact PCI 9U board 64 bit <2MHz VME FPGA ECL Drivers 128 bits ~20 MHz MBus 32 bits 66MHz (max) Local bus 64 bits 33 MHz PCI J1 J2 J3 J5 J4 PLX 9656 UII Drivers Clk(s)/ roms Run IIb strategy: purchase additional, more powerful commercial processors as late as reasonably possible.

DØ Collaboration Meeting October 10, Silicon Track Trigger for Run IIb  STT upgrade needed to u accommodate new L0? s New L0 fits within baseline Run IIb upgrade s even without L0, increase processing power for higher occupancy u Modest STT upgrade requires small quantity of same boards that are used in Run IIa. Readout layers 0,1,2,3,5 Technical Progress:  VME Transition Modules procured u Concern about obsolescence  Other procurements awaiting Layer 0 decision

DØ Collaboration Meeting October 10, Installation  Words here about trigger installation u want to install as early as possible s most benefits u want to install during machine shutdown s where do we need the most access  also repeat a little what we have in “the document” on installation

DØ Collaboration Meeting October 10, Summary  Lots of trigger progress and potential  Trigger workshop this weekend (Saturday/Sunday) u url  trigger upgrade is being redefined in light of run2b prospects u installation schedule u new project approval will be happening in the next month u workshop this weekend

DØ Collaboration Meeting October 10, Backup slides follow

DØ Collaboration Meeting October 10, Fake rate vs.luminosity  Even at modest occupancies, the high-p T single track trigger would fire at >15 kHZ Nominal 396 ns (1 high pT track) (1 high+1 medium pT) 396 ns Green points = Run IIa CTT Red points = Run IIb CTT

DØ Collaboration Meeting October 10, Run IIb L1CTT: Granularity  Use full fiber resolution to restrict roads Run IIaRun IIb

DØ Collaboration Meeting October 10, L1CalTrack System  Uses largely same hardware as existing L1muon u modest cost and effort required