1 Module and stave interconnect Rev. sept. 29/08.

Slides:



Advertisements
Similar presentations
Module design for B-layer replacement V.1. Bare Module dimensions mm Active area mm mm Footprint mm stack 200um chip 20um bumps.
Advertisements

ASE Flip-Chip Build-up Substrate Design Rules
2x2 module & stave layouts. 2 options “Small chip” “Big chip” Boundary between “small” and “big” is determined by the 6” sensor wafer layout that must.
Manchester 09/sept/2008A.Falou & P.Cornebise {LAL-Orsay}1 CALICE Meeting/ Manchester Sept 2008 SLAB Integration & Thermal Measurements.
P. Béné, F. Cadoux, A. Clark, D. Ferrère, C. Husi, M. Weber University of Geneva IBL General Week - 11, 12 February 2010 IBL Stave Loading Status Summary.
ATLAS Module building at Glasgow
Layer 0 Grounding Requirement in terms of noise performance Grounding/Shielding studies with L0 prototype Summary Kazu Hanagaki / Fermilab.
I.Tsurin Liverpool University 08/04/2014Page 1 ATLAS Upgrade Week 2014, Freiburg, April 7-11 I.Tsurin, P.Allport, G.Casse, R.Bates, C. Buttar, Val O'Shea,
November Vertex 2002 Kazu Hanagaki1 Layer 0 in D0 Silicon Tracker for run2b Kazu Hanagaki / Fermilab for D0 run2b Silicon Tracker group Motivation.
STATUS OF THE CRESCENT FLEX- TAPES FOR THE ATLAS PIXEL DISKS G. Sidiropoulos 1.
Embedded Pitch Adapters a high-yield interconnection solution for strip sensors M. Ullán, C. Fleta, X. Fernández-Tejero, V. Benítez CNM (Barcelona)
VELO upgrade electronics – HYBRIDS Tony Smith University of Liverpool.
M. Gilchriese Local Support R&D Update ATLAS Pixel Upgrade Meeting April 9, 2008 M. Cepeda, S. Dardin, M. Garcia-Sciveres, M. Gilchriese and R. Post LBNL.
SVX4 chip 4 SVX4 chips hybrid 4 chips hybridSilicon sensors Front side Back side Hybrid data with calibration charge injection for some channels IEEE Nuclear.
ATLAS Tracker Upgrade Stave Collaboration Workshop Oxford 6-9 February 2012 ABC 130 Hybrid.
13 Dec. 2007Switched Capacitor DCDC Update --- M. Garcia-Sciveres1 Pixel integrated stave concepts Valencia 2007 SLHC workshop.
17/06/2010UK Valencia RAL Petals and Staves Meeting 1 DC-DC for Stave Bus Tapes Roy Wastie Oxford University.
CVD PCB, first steps. 15 mm 25 mm Chip area. No ground plane underneath the chip. Bulk isolated => only one ground line Power lines Connector: 11,1mm*2,1mm:
ATLAS Upgrade ID Barrel: Services around ‘outer cylinder’ TJF updated According to the drawing ‘Preparation outer cylinder volume reservation’
1 Module and stave interconnect Rev. sept. 29/08.
1 Physics of Compressed Baryonic Matter 12 th CBM Collaboration Meeting R&D ON MICRO-CABLES FOR BABY SENSOR RADIATION TEST MODULE October , 2008.
High Density Interconnect (WBS 1.4.3) Extension Cables (WBS 1.4.4) Douglas Fields University of New Mexico Douglas Fields, FVTX DOE Review November 17,
1 WP3 Bi-Weekly Meeting Activities at Liverpool 1.Evaluation of Compact DCDC converter Designed to match up to an ABC130 module 2.Status of FIB’d hybrid/module.
M.Oriunno, SLAC Stave cable and module options. M.Oriunno, SLAC Background - module The IBL electrical unit for data output is a single chip The use of.
Columbia University IN THE CITY OF NEW YORK ROC3' / preproduction ROC Design Status E.J. Mannel StriPixel Review October 1, 2008.
PXL Cable Options LG 1HFT Hardware Meeting 02/11/2010.
Module Development Plan I believe that we are ready to proceed to a program to demonstrate a PS module based on “2.5 D” interconnections. This is based.
Andy Blue Glasgow Update. Andy Blue WP3 Meeting Summary ESD Protection –Part all arrived and installed Compressed Air Controls –New lines and panel being.
The Inclusive (Measurement ) FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08 FPIX Chip Module/Hybrid Testcard Pixel Plane Assembly/Integration.
1 4 PCB: LEFT TOP 115 channels, LEFT BOTTOM (115), RIGHT TOP (106), RIGHT BOTTOM (106). For LEFT TOP board 115 channels we have: 115 smd connectors (AMP.
Grounding Studies Metal box sensor SVX4/hybrid Analog cable GND(20W)
Low Mass Rui de Oliveira (CERN) July
Tevatron II: the world’s highest energy collider What’s new?  Data will be collected from 5 to 15 fb -1 at  s=1.96 TeV  Instantaneous luminosity will.
1 Outer Barrel, Phase 2 Mech Review 26 Aug 2013, indico: Antti Onnela, CERN Tracker Phase 2 Mechanics Review, 26 August 2013 Status of the Outer.
Proposal for the assembly of the PHOBOS ring counters (H.P. 3/20/98) I would like to propose and discuss with you an alternative layout and assembly procedure.
Hybrid circuits and substrate technologies for the CMS tracker upgrade G. Blanchot 04/MAY/2012G. Blanchot - WIT
Possible types of module Si/W CALORIMETER CONCEPT Si/W CALORIMETER CONCEPT G.Bashindzhagyan Moscow State University June 2002 Internal structure (not in.
D. M. Lee, LANL 1 07/10/07 Forward Vertex Detector Overview Technical Design Overview Design status.
WG3 – STRIP R&D ITS - COMSATS P. Riedler, G. Contin, A. Rivetti – WG3 conveners.
PS Module Ron Lipton, Feb A bit of History During much of the conceptual design phase of the outer tracker we had focused on the “long barrel”
EOS and type I Prototype Service Modules Mike Dawson (Oxford), Rob Gabrielczyk (RAL), John Noviss (RAL) 19 th January 2015 ATLAS Upgrade Activities, Oxford.
Integration of the MVD Demonstrator S. Amar-Youcef, A. Büdenbender, M. Deveaux, D. Doering, J. Heuser, I. Fröhlich, J. Michel, C. Müntz, C. Schrader, S.
15th January 2014 WP4 Meeting Oxford1 EoS PCB Mike Dawson University of Oxford.
Module Radiation Length. Goals Estimate the expected radiation length of a module, based on the design and measurements on as-built modules Determine.
DOE CD-2/3a Review of the BTeV Project – December 14-16, BTeV Pixel Detector Pixel Module Assembly and Half-Plane Assembly Guilherme Cardoso James.
1 FANGS for BEAST J. Dingfelder, A. Eyring, Laura Mari, C. Marinas, D. Pohl University of Bonn
Mauro Citterio Milano, PP2/Services - an update - Mauro Citterio INFN Milano Type II cables  Layout in progress  Duplication of VVDC wires.
2 March 2012Mauro Citterio - SVT Phone meeting1 Peripheral Electronics Some updates Mauro Citterio INFN Milano.
Andrei Nomerotski 1 Flex Status & AID A.Nomerotski, 18 June 2010.
Stave Emulator for sLHC Prototyping L. Gonella, A. Eyring, F. Hügging, H. Krüger Physikalisches Institut, Uni Bonn.
EC: 7 DISK concept Preliminary considerations
De Remigis The test has been accomplished with an SLVS signal, since that was chosen for the serial communication between the readout and the optical converter.
Berkeley status Aug 10th, 2012.
SVD Electronics Constraints
n-XYTER Hybrid Developments
ATLAS pixel module assembly flow
T. Bowcock University of Liverpool
Status and plans for the pigtails
Grid Pix Field Simulations and precision needed for a module
Hybrid Pixel R&D and Interconnect Technologies
ob-fpc: Flexible printed circuits for the alice tracker
Strawman module design
HPS Motherboard Electronic Design
SIT AND FTD DESIGN FOR ILD
AMS-CHESS-1 daughterboard – bonding diagram
Flex Status A.Nomerotski, 4 May 2010.
Outer Endcap External Bus tape
Possible types of Si-sensor: SILICON CALORIMETRY FOR A LINEAR COLLIDER G.Bashindzhagyan, Il Park August Silicon sensor.
Presentation transcript:

1 Module and stave interconnect Rev. sept. 29/08

2 Outer Stave layout … End of stave card serves 8 modules (half a stave) along Z Stave has 32 modules total, 16 on each face. 8 modules connected to 1 stave card via stave cable. Cable is pre-assembled on stave (4 cables per stave). Modules are loaded on top of cable and connected down to it with a connector similar to present PP0 connector, but smaller. Module on back

3 4-chip outer stave module Active area Flex pigtail (connector plugs into page)‏ Pixel orientation Flex down to chip w-bonds Flex hybrid on top of sensor

4 Loaded module side view 20 position connector would be used. Replace dimension by 6.52 glue chips sensor flex connector Compressed scale 1.0 mm stiffener Hirose DF30 series 0.4mm contact pitch

5 12mm1.5mm X8 HV-ret HV-1-2 HV-3-4 HV-5-6 NTC Out-1 Out-2 HV-7-8 Multi- drops Layer 1: Signals (1/4 oz copper)‏ Layer 2: Power and return (25um aluminum)‏ ground ref. +LV x8 DC-DC Stave cable layout -LV x8 (trace width varies such that each module sees the same cable resistance)‏...

6 Stave section (not to scale)‏ Center line glue Polyimide substrate inter-layer cover layer aluminum copper chips sensor glue facing foam Flex hybrid

7 Power parameters 3.390% efficient DCDC module power excluding sensor bias (W)‏ 0.34Cable power dissipation (average per module in W)‏ 0.34Stave cable round-trip voltage drop before DCDC convert. (V)‏ 220Number of squares 1-way (same for all modules)‏ Aluminum layer resistance per square (ohm)‏ 2.0Single module 1.5V chip combined current (A)‏ 3.8stave cable metal width (cm) 25Stave cable aluminum thickness (um)‏ These are nominal values without contingency Single module stave cable current with DC-DC (A)‏ 1.0

8 Inner layer modules For small radius the staves must be narrow => single-chip-wide modules. Probably want single sided staves also. If sensors are 3D they can naturally have active edges Once active edge sensors are used, single-chip modules are very attractive –No active fraction advantage for bigger modules –High data rates also prefer single chip modules One serial output per chip –(may still not be enough for BL)‏

9 Single chip module features Simplified assembly process –no single chip probing needed before flip-chip –No flex hybrid Test individual modules with a probe card Load “bare modules” directly on stave cable Inherently high yield SC stave module concept from US Upgrade meeting, Dallas 2004: robotically placed, fully tested 1-chip modules. Wire bond to stave after placement. End of stave card

10 But… Stave cable is more challenging. –Not as much room as on outer staves –4 times as many data output lines needed (at least)‏ Inner stave cable concept (presented in BL replacement meeting sept. 2007) Cable stack Pre-laminated on bare stave Cable stack with 24 flaps before lamination (half stave). End of stave card could be built-in Flap folds over after module is glued