“Performance Model for Inter-chip Busses”1 Performance Model for Inter-chip Busses Considering Bandwidth and Cost ISCAS 2005 Authors: Brock J. LaMeres University of Colorado, Boulder, CO Sunil P. Khatri Texas A&M University, College Station, TX.

“Performance Model for Inter-chip Busses”2 Problem : Packaging Limits Performance Transistor Technology is Faster than Package Technology IC “Moore’s Law” - # of transistors will double every 18 months Package “Rent’s Rule” - # of I/O will double in next 10 years

“Performance Model for Inter-chip Busses”3 Inductive noise in packaging Package performance model – Relationship with inductive parasitics – “Bandwidth per unit cost” metric Experimental results – Model versus SPICE Conclusions Outline

“Performance Model for Inter-chip Busses”4 1) Supply Bounce Switching current through inductive packaging induces voltage: Multiple Signals Switching Increase the Problem: Inductive Noise in Packaging n = # of drivers sharing the power/gnd pin (L 11 ). L 11 = Inductance of pwr/gnd pin that current is being switched through.

“Performance Model for Inter-chip Busses”5 2) Pin-to-Pin Coupling Switching Signals Couple Voltage onto Neighbors: Multiple Signals Switching Increase the Problem: Inductive Noise in Packaging M 1k = Mutual Inductance between pwr/gnd pin and k th signal pin.

“Performance Model for Inter-chip Busses”6 Analytical Model Bus Parameters W BUS : # of signals in the bus GSPSSSGSSPSSGSSPSS W BUS N G : # of Grounds in the bus GSPSSSGSSPSSGSSPSS

“Performance Model for Inter-chip Busses”7 Analytical Model Bus Parameters SPG : (# of Signals) : (# of PWR’s) : (# of GND’s) = 4:1:1 in above example GSPSSSGSSPSSGSSPSS Repetitive Pattern of Signal, Power, and Ground Pins

“Performance Model for Inter-chip Busses”8 Analytical Model Bus Performance Description dt dv v(t) t Slewrate

“Performance Model for Inter-chip Busses”9 Analytical Model Bus Performance Description v(t) t Risetime (0.8)  V DD 90% 10% V DD

“Performance Model for Inter-chip Busses”10 DATA Analytical Model Bus Performance Description DATA Minimum Unit Interval UI

“Performance Model for Inter-chip Busses”11 Analytical Model Bus Performance Description DATA Bus Throughput DATA Tx W BUS Rx

“Performance Model for Inter-chip Busses”12 NOISE Analytical Model Bus Performance Limits v(t) t Maximum Acceptable Ground Bounce p  V DD V DD (p typical = 5%)

“Performance Model for Inter-chip Busses”13 Analytical Model Model Development Maximum Ground Bounce Self Contribution Coupling Contribution

“Performance Model for Inter-chip Busses”14 Analytical Model Model Development Maximum Slewrate - pull out (di/dt) - convert to (dv/dt)

“Performance Model for Inter-chip Busses”15 Analytical Model Model Development Minimum Risetime : But since - convert slewrate to risetime

“Performance Model for Inter-chip Busses”16 Analytical Model Model Development Maximum Datarate : Also, since - convert Risetime to Datarate Maximum Throughput : Finally, we have

“Performance Model for Inter-chip Busses”17 Experimental Results Per-pin and Bus throughput values computed for 3 packages – Compared our model with SPICE simulations QFP – Wire Bond BGA – Wire Bond BGA – Flip-Chip

“Performance Model for Inter-chip Busses”18 Experimental Results QFP Wire-Bond Package Simulations Per-Pin Data-RateBus Throughput - Throughput reaches an asymptotic limit as channels are added Model Simulation

“Performance Model for Inter-chip Busses”19 Experimental Results BGA Wire-Bond Package Simulations Per-Pin Data-RateBus Throughput - Level 1 : BGA Increases Performance Over QFP

“Performance Model for Inter-chip Busses”20 Experimental Results BGA Flip-Chip Package Simulations Per-Pin Data-RateBus Throughput - Level 2: Flip-Chip Increases Performance Over Wire-Bond

“Performance Model for Inter-chip Busses”21 Experimental Results Cost Must Also Be Considered in Analysis Bandwidth Per Cost This Metric Represents “Cost Effectiveness of the Bus” Units = (Mb/$)

“Performance Model for Inter-chip Busses”22 Experimental Results Bandwidth Per Cost Results Faster Narrower Busses = More Cost Effective

“Performance Model for Inter-chip Busses”23 Presented a model for bus performance – Accounts for inductive parasitics in packaging – Developed a “bandwidth-per-unit-cost” metric to evaluate packages Experiments indicate – Strong agreement with SPICE simulation – Throughput for a bus reaches asymptotic limit as channels added Increase in channels compensated by decrease in per-pin throughput Optimal number of channels is small (4-8) “Bandwidth-per-unit-cost” experiments indicate – Flip-chip packages are actually most cost-effective – Narrower buses have better bandwidth-per-unit-cost Conclusions

“Performance Model for Inter-chip Busses”24 Thank you!

“Performance Model for Inter-chip Busses”25 Backup Slides

“Performance Model for Inter-chip Busses”26 Example PACKAGE - Rent’s Rule IC Core - Moore’s Law On-Chip - 8 bit Data Bus Mb/s Package - Need (8)(300M) = 2400 Mb/s

“Performance Model for Inter-chip Busses” Mb/s Example Need: QFP – Wire Bond BGA – Wire Bond BGA – Flip-Chip - 4 bits wide, SPG=2:1:1 - 1 bit wide, SPG=2:1:1 - 1 bit wide, SPG=2:1: bits wide, SPG=4:1:1 - 1 bit wide, SPG=4:1:1 - 1 bit wide, SPG=8:1:1 X XX X

“Performance Model for Inter-chip Busses”28 Example Cost of Each Bus Configuration Most Cost Effective: - BGA-WB - W bus = 1 - SPG = 2:1:1

“Performance Model for Inter-chip Busses”29 Experimental Results Cost per Bus Configuration Performance Increases with Cost (Package, SPG) $