Senior Capstone Project: Fast Tuning Synthesizer Member: Nathan Roth Advisors: Dr. Huggins Dr. Shastry Mr. James Jensen Date:March 4, 2004

Presentation Outline Project Summary Functional Description Detailed Description Review of Previous Work Laboratory Results Semester Schedule

Project Summary Creation of a frequency synthesizer –Use of direct synthesis approach

Project Summary System Characteristics –Output Frequencies of 3650, 3700, 3850, 3900, 4450, 4500, 4650, and 4700 MHz –Output Power of 0 dBm, ± 3 dB –Output Spurs < -45 dBc –Tuning Time < 500 ns, 200 ns if possible –Use of an External 100 MHz Reference Signal

Functional Description Fast Tuning Frequency Synthesizer 3.6 – 4.6 GHz 100 MHz Reference D2 D1 D0 Digital Input Command Desired Output Frequency

Detailed Description

Input Module

Resolution Modules

Basis Frequency Modules

Switch Selection Module

Output Module

Laboratory Work - Review Designed and Simulated Ideal Chebyshev Filters –Used Insertion Loss Method –Developed Low-Pass Filter Prototype –Transformed to Band-Pass Filter Added Parasitic Effects –Real Component Values –Real Inductor Responses –Microstrip Transmission Effects –Via Connections

Laboratory Work - Review

Determined and Ordered Necessary Parts

Laboratory Work Created PCB Layouts for Filter Boards Fabricated, Populated, and Tested Filter Boards Developed Modular Layout Plan Currently Creating PCB Layouts for Components

Laboratory Work

Dark Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Aqua Blue = S21 Actual Blue/Purple = S11 Actual

Laboratory Work Dark Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Aqua Blue = S21 Actual Blue/Purple = S11 Actual

Laboratory Work Aqua Blue = Ideal Dark Blue = S21 Simulated Red = S11 Simulated Purple = S21 Actual Blue/Purple = S11 Actual

Laboratory Work Aqua Blue = Ideal Red = S21 Simulated Dark Blue = S11 Simulated Purple = S21 Actual Blue/Purple = S11 Actual

Laboratory Work Light Blue = Ideal Red = S21 Simulated Aqua Blue = S11 Simulated Dark Blue = S21 Actual Purple = S11 Actual

Laboratory Work Aqua Blue = Ideal Purple = S21 Simulated Red = S11 Simulated Dark Blue = S21 Actual Light Blue = S11 Actual

Laboratory Work

Preliminary Spring Semester Schedule WeekTask Winter BreakResearch and understand phase locked loop (PLL) theory and circuitry Begin design of PLL system Finalize filter design and simulations Begin implementing as parts arrive Full scale simulation of direct synthesis (DS) system Jan 19 – 25Design of PLL system DS system simulation Jan 26 – Feb 1Design PLL system DS system simulation Have all filters tested and built Feb 2 – 8Complete design of PLL system DS system simulation Feb 9 – 15Simulation of PLL system Complete DS system Simulation

Preliminary Spring Semester Schedule Feb 9 – 15Simulation of PLL system Complete DS system Simulation Feb 16 – 22Simulation of PLL system Feb 23 – 29Complete simulation of PLL system March 1 – 7Components Arrive, Begin Soldering, Testing, and Biasing Components March 8 – 14Physical implementation of DS March 15 – 21Physical implementation of DS, Spring Break? March 22 – 28Begin DS full scale testing March 29 – April 4DS full scale testing April 5 – 11Complete DS full scale testing April 12 – 18 April 19 – 25Student Expo April 26 – May 2Present successful findings

Revised Spring Semester Schedule March 1 – 7Generate PCB Layout for Components March 8 – 14Fabricate PCBs March 15 – 21Spring Break/Fabricate PCBs March 22 – 28Solder Components to PCBs March 29 – April 4System Testing April 5 – 11System Testing April 12 – 18 System Testing April 19 – 25System Testing/Student Expo April 26 – May 2Present successful findings

Delay Line Correlator Voltage output proportional to cos (wT) Power Splitter T L R I Cos (wt) RF cable with measure time delay = T

Fast Tuning Synthesizer Any questions?