Accurate Pseudo-Constructive Wirelength and Congestion Estimation Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Xu Xu, UCSD CSE Dept., La Jolla Supported.

Slides:



Advertisements
Similar presentations
Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD.
Advertisements

Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December.
Placer Suboptimality Evaluation Using Zero-Change Transformations Andrew B. Kahng Sherief Reda VLSI CAD lab UCSD ECE and CSE Departments.
Toward Better Wireload Models in the Presence of Obstacles* Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu and Dirk Stroobandt† UC San Diego CSE Dept. †Ghent.
Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator Andrew B. KahngSherief Reda VLSI CAD Laboratory.
International Conference on Computer-Aided Design San Jose, CA Nov. 2001ER UCLA UCLA 1 Congestion Reduction During Placement Based on Integer Programming.
On Mismatches Between Incremental Optimizers and Instance Perturbation in Physical Design Tools Andrew B. Kahng and Stefanus Mantik UCSD CSE & ECE Depts.,
Power-Aware Placement
On the Relevance of Wire Load Models Kenneth D. Boese, Cadence Design Systems, San Jose Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Stefanus Mantik,
Stability and Scalability in Global Routing S. K. Han 1, K. Jeong 1, A. B. Kahng 1,2 and J. Lu 2 1 ECE Department, UC San Diego 2 CSE Department, UC San.
Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory
Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu,
Local Unidirectional Bias for Smooth Cutsize-delay Tradeoff in Performance-driven Partitioning Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts. Work supported.
On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.
Placement Feedback: A Concept and Method for Better Min-Cut Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La.
On Legalization of Row-Based Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093
Yield- and Cost-Driven Fracturing for Variable Shaped-Beam Mask Writing Andrew B. Kahng CSE and ECE Departments, UCSD Xu Xu CSE Department, UCSD Alex Zelikovsky.
1 A Tale of Two Nets: Studies in Wirelength Progression in Physical Design Andrew B. Kahng Sherief Reda CSE Department University of CA, San Diego.
University of Toronto Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto)
Estimation of Wirelength Reduction for λ-Geometry vs. Manhattan Placement and Routing H. Chen, C.-K. Cheng, A.B. Kahng, I. Mandoiu, and Q. Wang UCSD CSE.
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
ISPD 2000, San DiegoApr 10, Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent.
Interconnect Implications of Growth-Based Structural Models for VLSI Circuits* Chung-Kuan Cheng, Andrew B. Kahng and Bao Liu UC San Diego CSE Dept.
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Cost-Based Tradeoff Analysis of Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University.
Congestion Estimation in Floorplanning Supervisor: Evangeline F. Y. YOUNG by Chiu Wing SHAM.
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Accuracy-Configurable Adder for Approximate Arithmetic Designs
MASSOUD PEDRAM UNIVERSITY OF SOUTHERN CALIFORNIA Interconnect Length Estimation in VLSI Designs: A Retrospective.
CRISP: Congestion Reduction by Iterated Spreading during Placement Jarrod A. Roy†‡, Natarajan Viswanathan‡, Gi-Joon Nam‡, Charles J. Alpert‡ and Igor L.
Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research Andrew B. Kahng, Hyein Lee and Jiajia Li UC San Diego VLSI CAD Laboratory.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
1 Wire Length Prediction-based Technology Mapping and Fanout Optimization Qinghua Liu Malgorzata Marek-Sadowska VLSI Design Automation Lab UC-Santa Barbara.
Jason Cong‡†, Guojie Luo*†, Kalliopi Tsota‡, and Bingjun Xiao‡ ‡Computer Science Department, University of California, Los Angeles, USA *School of Electrical.
IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing © KLMH Lienig 1 What Makes a Design Difficult to Route Charles.
GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction David Yeager Darius Chiu Guy Lemieux The University of British.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
ECE 260B – CSE 241A /UCB EECS Kahng/Keutzer/Newton Physical Design Flow Read Netlist Initial Placement Placement Improvement Cost Estimation Routing.
Chris Chu Iowa State University Yiu-Chung Wong Rio Design Automation
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University.
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
International Symposium on Physical Design San Diego, CA April 2002ER UCLA UCLA 1 Routability Driven White Space Allocation for Fixed-Die Standard-Cell.
Dept. of Electronics Engineering & Institute of Electronics National Chiao Tung University Hsinchu, Taiwan ISPD’16 Generating Routing-Driven Power Distribution.
Dirk Stroobandt Ghent University Electronics and Information Systems Department Multi-terminal Nets do Change Conventional Wire Length Distribution Models.
EE4271 VLSI Design VLSI Channel Routing.
6/19/ VLSI Physical Design Automation Prof. David Pan Office: ACES Placement (3)
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
Prediction of Interconnect Net-Degree Distribution Based on Rent’s Rule Tao Wan and Malgorzata Chrzanowska- Jeske Department of Electrical and Computer.
On the Relevance of Wire Load Models
Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts.
Revisiting and Bounding the Benefit From 3D Integration
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
Continuous Density Queries for Moving Objects
Presentation transcript:

Accurate Pseudo-Constructive Wirelength and Congestion Estimation Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Xu Xu, UCSD CSE Dept., La Jolla Supported by MARCO GSRC

Outline  Wirelength and Congestion Estimation Previous Work and Our Contribution New Wire Density Model Estimate Detoured Nets Experimental Confirmation Conclusion and Future Work

Wirelength and Congestion Estimation Wirelength and Congestion Estimation Problem Given: A placed VLSI standard-cell design Estimate: Total wirelength and congestion (0, 0) (n, m) BB(t) Wire density D t (x,y) = probability that line segment  BB(t) will be used in the routed path BB(t) = Bounding box of net t

Outline Wirelength and Congestion Estimation  Previous Work and Our Contribution New Wire Density Model Estimate Detoured Nets Experimental Confirmation Conclusion and Future Work

Previous Works and Our Contribution Lou et al. (ISPD-2001) assume that every path has the same probability of occurrence Typical Path  We assume that paths with smaller number of bends have larger probability of occurrence Typical Path

Previous Works and Our Contribution Previous probabilistic methods ignore detouring  We take detouring into account so that the predicted congestion map can better fit actual routing results Detoured Path

Previous Works and Our Contribution Previous congestion map constructions are “one-shot”  We give an iterative congestion map construction by considering the interaction between nets. Routing probability distributions are the same. 

Outline Wirelength and Congestion Estimation Previous Work and Our Contribution  New Wire Density Model Estimate Detoured Nets Experimental Confirmation Conclusion and Future Work

New Wire Density Model Goal: Set up a more practical model for congestion estimation Instead of assuming that all paths have the same probability of occurrence  We assume that only paths with the same number of bends have the same probability of occurrence Only consider horizontal line segments Blockage effects and detouring not included (will be handled later) p b = Probability of b-bend paths η = 0.6

New Wire Density Model w = Multi-bend factor b=1 b=2b=3b=4

Blockage Effect Model Every path must pass exactly one of line segments in S. Blockage S t’ x, y

Test New model 20

Outline Wirelength and Congestion Estimation Previous Work and Our Contribution New Wire Density Model  Estimate Detoured Nets Experimental Confirmation Conclusion and Future Work

Two Questions to Answer Which nets will detour? How to predict detoured wirelength?

Relationship Between Congestion and Detouring 200 Layout 200 Only detoured nets are counted Detoured nets are around congested regions.

Congestion_Factor C(x, y) = Congestion of (x, y) F(t) = Half-perimeter of BB(t) Detour length # of netsAvg. Congestion Factor [0, 10] [10, 20] [20, 30] [30, 40] [40, 50] [50, 60] [60, 300] Good indictor for which nets will detour Hard to estimate the detoured wirelength, since detoured wirelength also depends on the region outside BB(t).

Iterative Estimation Method If Congestion_Factor(t) > a  Expand the net bounding box in the least congested direction in order to reduce Congestion_Factor(t)  Recalculate wire density function and Congestion_Factor(t) for detoured nets Keep expanding until Congestion_Factor(t) < a for all nets Need a model for detoured nets expand

Detoured Nets Model Main idea: mapping the detoured paths in an n x m grid to paths without detouring in an expanded (n+2l) x m grid. x=n+l must be passed. l l = Detoured wirelength (n+l, y 0 ) (x, y)  (x, y) if y<y 0  (n+2l-x, y) otherwise

Detoured Nets Model p d,b = Probability of b-bend detoured paths b=2b=3b=4

Congestion_Factor Based Algorithm Input : Placed netlist with fixed pin location Output : Total wirelength and congestion map For each net in the layout For each line segment calculate wire density and update its congestion For each net t in the layout calculate Congestion_Factor(t) While (the maximum of Congestion_Factor > a) expand BB(t) by 1 grid in the least congested direction recalculate the Congestion_Factor(t)

Outline Wirelength and Congestion Estimation Previous Work and Our Contribution New Wire Density Model Estimate Detoured Nets  Experimental Confirmation Conclusion and Future Work

Experimental Setup Five industry designs obtained as LEF/DEF files Divide the layout into equal regions Output includes total wirelength and congestion Output results are compared with actual routing results of a commercial detailed router, Cadence WarpRoute

Comparison of Total Wirelength % E % D % C % B % A CPUimproveEst. WL Congestion_Factor Based Actual_WLRSMT_WLTest case

Comparison of Estimation Quality CPU   New Model +Con_Fac CPU   New Model CPU   Lou’s Model EDCBATestcase Ideal values:  =1 and  =0 Metrics proposed in Kannan et al. DAC-2002

Comparison of Congestion Maps Estimated Actual Layout 200 Layout 200

Outline Wirelength and Congestion Estimation Previous Work and Our Contribution New Wire Density Model Estimate Detoured Nets Experimental Confirmation  Conclusion and Future Work

Conclusions / Future Work New, accurate wirelength and congestion estimation methods Improve the wirelength estimation accuracy by 90% on average with respect to the traditional RSMT wirelength estimate More accurate congestion maps than current estimation methods Include new estimator into a placer