CSE 140 Discussion Section Midterm #2 Review Mingjing Chen

Flip-Flops Conversion Implement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. S R Q Q’ Combinational logic J K JK flip-flop Solve the combinational logic design problem S = f 1 (J, K, Q) R = f 2 (J, K, Q)

Flip-Flops Conversion How to attain the specification of the combinational circuit? SRQQ’ 00Q prev Q’ prev S = f 1 (J, K, Q) R = f 2 (J, K, Q) JKQQ’ 00Q prev Q’ prev Q prev JK QSR Truth table for combinational logic 0 x x 0 x 0 0 x

Flip-Flops Conversion JKQ prev QSR Truth table for combinational logic 0 x x 0 x 0 0 x x00x JK Q prev Kmap for S S = J Q’ prev xx JK Q prev Kmap for R R = K Q prev S R Q Q’ K J

Sequential Circuit Design A state machine is described by the following state equations. (1). Write the state table. 2-bit states: Q 1, Q 0 1 input: x 1 output: y XQ1(t)Q0(t)Q1(t+1)Q0(t+1)y

Sequential Circuit Design Design the system with two JK flip-flops and a minimal AND-OR-NOT network. XQ1(t)Q0(t)Q1(t+1)Q0(t+1)J1K1J0K0y X 1X x1 x0 1X 0X x0 x1 0X x1 1X x0 0X x0 0X x0

Sequential Circuit Design XQ1(t)Q0(t)J1K1J0K0y X 1X x1 x0 1X 0X x0 x1 0X x1 1X x0 0X x0 0X x0 xx01 xx Q1Q0 X Kmap for J1 J 1 = X’Q 0 +XQ 0 ’ 01xx 10xx Q1Q0 X Kmap for K1 K 1 = X’ Q 0 ’+X Q 0 0xx0 1xx Q1Q0 X Kmap for J0 x00x x01x Q1Q0 X Kmap for K0 J 0 = X’Q 1 K 0 = X’ Q 1 ’ Q1Q0 X Kmap for y y = Q 1 ’+Q 0

Timing Circuit implemented using two T flip-flops and a D flip-flop. Timing characteristics:  T flip-flop: clock-to-Q maximum delay tpcq = 2ns clock-to-Q minimum delay tccq = 1.8ns setup time tsetup = 1ns hold time thold = 1.5ns  D flip-flop: clock-to-Q maximum delay tpcq = 2.5ns clock-to-Q minimum delay tccq = 2.3ns setup time tsetup = 2.5ns hold time thold = 2ns  NAND gate: propagation delay tpd = 1ns contamination delay tcd = 0.8ns  Inverter: propagation delay tpd = 0.5ns contamination delay tcd = 0.3ns

Timing TQ TQ DQ How many paths?

Timing TQ TQ DQ 3 paths P1 P2 P3

Timing What is the maximum clock frequency of this circuit? P1: tpcq(D) + tpd(NAND) + tsetup(T) <= clock cycle P2: tpcq(T) + tpd(NOT) + tsetup(D) <= clock cycle P3: tpcq(T) + tpd(NAND) + tsetup(T) <= clock cycle <= clock cycle <= clock cycle <= clock cycle Min cycle = 5 ns  max f = 1 / min cycle = 200 MHz

Timing what is the maximum clock skew that the circuit can tolerate before it might experience a hold time violation? P1: tccq(D) + tcd(NAND) >= thold(T) + skew P2: tccq(T) + tcd(NOT) >= thold(D) + skew P3: tccq(T) + tcd(NAND) >= thold(T) + skew >= skew >= 2 + skew >= skew Max skew = 0.1ns

Decoder & MUX three-input Boolean function f(a, b, c) = ∑Pm(1, 2, 4, 7) + ∑ Pd(3) 01x ab c f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c)

Decoder & MUX Implement the function using a minimal network of 2:4 decoders and OR gates f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ s1s1 s0s s1s1 s0s0 In c a b a b If inverter is not allowed f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’(b+c)+a(b+c)’+bc s1s1 s0s s1s1 s0s0 In c a b 1 1 c b

Decoder & MUX Implement the function using a minimal network of 4:1 multiplexers. f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ s1s1 s0s0 a b Out c c’ c

Decoder & MUX Implement the function using a minimal network of 2:1 multiplexers f = a’c+a’b+bc+ab’c’ = af(1, b, c) + a’f(0, b, c) = a(bc+b’c’) + a’ (b+c) a 1 0 s b 1 0 s c c’ b 1 0 s 1 c