EECC250 - Shaaban #1 lec #12 Winter99 1-14-2000 Serial Communication ASCII Character Parity BitFrom68000 ASCII Character Parity Bit Transmitter Buffer.

Slides:



Advertisements
Similar presentations
Serial Interface Dr. Esam Al_Qaralleh CE Department
Advertisements

INPUT-OUTPUT ORGANIZATION
11-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL I/O System Design.
Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology I/O System Design.
The 8051 Microcontroller Chapter 5 SERIAL PORT OPERATION.
Interrupts Chapter 8 – pp Chapter 10 – pp Appendix A – pp 537 &
1 Homework Reading –Tokheim, Section 13-6 Continue mp1 –Questions? Labs –Continue labs with your assigned section.
I/O Unit.
Serial I/O - Programmable Communication Interface
Asynchronous Communication Hardware  Data within a DTE is usually stored and moved in a parallel fashion.  Data sent across the channel is generally.
Implementing interrupt driven IO. Why use interrupt driven IO? Positive points –Allows asynchronous operation of IO events –Good use of resources –Leads.
Serial Input/Output Interface Outline –Serial I/O –Asynchronous serial I/O –6850 ACIA –68681 DUART –Synchronous serial I/OInterface Standards –68000 Serial.
EECC250 - Shaaban #1 lec #13 Winter HEX DEC CHR Ctrl 00 0NUL 01 1 SOH ^A 02 2STX ^B 03 3ETX ^C 04 4EOT ^D 05 5ENQ ^E 06 6ACK ^F 07 7BEL.
PC Modem Control The 8250 UART supplied with the PC supports a limited number of RS-232-C modem functions: The UART can be programmed to interrupt the.
Eng. Husam Alzaq The Islamic Uni. Of Gaza
EECC250 - Shaaban #1 Lec # 4 Winter Computer Input and Output (I/O) One of the basic and essential features designed in a computer system is.
7-1 Digital Serial Input/Output Two basic approaches  Synchronous shared common clock signal all devices synchronised with the shared clock signal data.
1 The 9-Pin Connector Pin abbreviations (numbers in parentheses are the 25D pin numbers): 1. CD (8) 2. RD (Rx) (3) 3. TD (Tx) (2) 4. DTR (20) 5. SG (Ground)
GURSHARAN SINGH TATLA PIN DIAGRAM OF 8085 GURSHARAN SINGH TATLA
ECE 371- Unit 11 Introduction to Serial I/O. TWO MAJOR CLASSES OF SERIAL DATA INTERFACES ASYNCHRONOUS SERIAL I/O - USES “FRAMING BITS” (START BIT AND.
Unit-5 CO-MPI autonomous
INPUT-OUTPUT ORGANIZATION
Computers in Surveying SVY2301 / E4006 Automated Surveying.
Khaled A. Al-Utaibi  Intel Peripheral Controller Chips  Basic Description of the 8255  Pin Configuration of the 8255  Block Diagram.
Serial Port I/O Serial port sends and receives data one bit at a time. Serial communication devices are divided into: Data Communications Equipment (DCE),
BIOS1 Basic Input Output System BIOS BIOS refers to a set of procedures or functions that enable the programmer have access to the hardware of the computer.
Input/Output mechanisms
UART and UART Driver B. Ramamurthy.
BIOS1 Basic Input Output System BIOS BIOS refers to a set of procedures or functions that enable the programmer have access to the hardware of the computer.
Lecture Set 9 MCS-51 Serial Port.
Dept. of Computer Science Engineering Islamic Azad University of Mashhad 1 DATA REPRESENTATION Dept. of Computer Science Engineering Islamic Azad University.
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
“Describe the overview of hardware interfacing and the serial communication interface. Describe the PIC18 connections to RS232. Explain the serial port.
Universal Asynchronous Receiver/Transmitter (UART)
Microprocessors 2 lesson Subjects lesson 7 Planning Interrupts Serial communication /USART Questions.
Serial Communications
Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Input/Output Organization.
Advanced Microprocessor1 I/O Interface Programmable Interval Timer: 8254 Three independent 16-bit programmable counters (timers). Each capable in counting.
Example. SBUF Register SCON Register(1) SCON Register(2)
 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.  Programmable peripheral designed for synchronous.
NS Training Hardware. Serial Controller - UART.
Universal Asynchronous Receiver/Transmitter (UART)
Interfaces and Synchronization Martin Weiss. EIA 232D Interface Standard u Synonymous with ITU V.24 u Asynchronous interface u Up to 19.2kbps u 50 foot.
Serial Communications Interface Module Slide #1 of 19 MC68HC908GP20 Training PURPOSE -To explain how to configure and use the Serial Communications Interface.
Extended Uart The High Speed Digital Systems Laboratory, Electrical Engineering Faculty, Technion By: Marganit Fina Supervisor: Rivkin Ina Winter 2007/8.
Systems Architecture, Fourth Edition 1 Data Representation Chapter 3.
بسم الله الرحمن الرحيم MEMORY AND I/O.
8251 USART.
DEPARTMENT OF ELECTRONICS ENGINEERING
BASICS OF SERIAL COMMUNICATIONS BIRLA VISHWKARMA MAHAVIDYALAYA ELECTRONICS & TELECOMMUNICATION DEPARTMENT PRESENTING BY: ABHISHEK SINGH AMANDEEP.
Tiva C TM4C123GH6PM UART Embedded Systems ECE 4437 Fall 2015 Team 2:
Machine level representation of data Character representation
Serial mode of data transfer
Homework Reading Continue mp1 Labs Tokheim, Section 13-6 Questions?
CS-401 Computer Architecture & Assembly Language Programming
BVM Engineering College Electrical Engineering Department : Microprocessor and Microcontroller Interfacing Interrupts of 8051 Prepared by:
E3165 DIGITAL ELECTRONIC SYSTEM
8253 Timer In software programming of 8085, it has been shown that a delay subroutine can be programmed to introduce a predefined time delay. The delay.
UART Serial Port Programming
UART Serial Port Programming
Serial Communication Interface: Using 8251
Serial Communication Interface
ASCII Character Codes nul soh stx etx eot 1 lf vt ff cr so
X1 & X2 These are also called Crystal Input Pins.
8259 Programmable Interrupt Controller
Number Systems Lecture 2.
CHAPTER SERIAL PORT PROGRAMMING. Basics of Serial Communication Computers transfer data in two ways: ◦ Parallel  Often 8 or more lines (wire.
RS-232 Port Discussion D12.1.
PIC Serial Port Interfacing
PIC Serial Port Interfacing
Presentation transcript:

EECC250 - Shaaban #1 lec #12 Winter Serial Communication ASCII Character Parity BitFrom68000 ASCII Character Parity Bit Transmitter Buffer (TB) Transmit ASCII Character Parity Bit To ASCII Character Parity Bit Receiver Buffer (RB)Receive Universal Asynchronous Receiver/Transmitter (UART) To device From device

EECC250 - Shaaban #2 lec #12 Winter HEX DEC CHR Ctrl 00 0NUL 01 1 SOH ^A 02 2STX ^B 03 3ETX ^C 04 4EOT ^D 05 5ENQ ^E 06 6ACK ^F 07 7BEL ^G 08 8BS ^H 09 9HT ^I 0A 10LF ^J 0B 11VT ^K 0C 12FF ^L 0D 13CR ^M 0E 14SO ^N 0F 15SI ^O 10 16DLE ^P 11 17DC1 ^Q 12 18DC2 ^R 13 19DC3 ^S 14 20DC4 ^T 15 21NAK ^U 16 22SYN ^V 17 23ETB ^W 18 24CAN ^X 19 25EM ^Y 1A 26SUB ^Z 1B 27ESC 1C 28FS 1D 29GS 1E 30RS 1F 31US HEX DEC CHR 20 32SP 21 33! 22 34” 23 35# 24 36$ 25 37% 26 38& 27 39’ 28 40( 29 41) 2A 42* 2B 43+ 2C 44, 2D 45- 2E 46. 2F 47/ A 58 : 3B 59 ; 3C 60 < 3D 61 = 3E 62 > 3F 63 ? HEX DEC CHR A B C 44 68D 45 69E F 47 71G 48 72H I 4A 74 J 4B 75 K 4C 76L 4D 77M 4E 78N 4F 79O 50 80P 51 81Q 52 82R 53 83S 54 84T 55 85U 56 86V 57 87W 58 88X 59 89Y 5A 90Z 5B 91[ 5C 92\ 5D 93] 5E 94^ 5F 95_ HEX DEC CHR 60 96` 61 97a 62 98b 63 99c d e f g h I 6A 106j 6B 107k 6C 108 l 6D 109m 6E 100n 6F 111o p q r s t u v w x y 7A 122 z 7B 123 { 7C 124| 7D 125 } 7E 126 ~ 7F 127DEL ASCII Code Table

EECC250 - Shaaban #3 lec #12 Winter Full-Duplex Serial Communication Lines External Receiver Lines:External Receiver Lines: –RxRTS* Low if local device can receive a character (connected to remote CTS*) –RxD Actual serial data received from remote device on this line. Transmitter Lines:Transmitter Lines: –TxRTS Request To Send: indicates local device is ready to transmit a character –TxD Actual serial data transmitted to remote device on this line –CTS* Cleared To Send: Low indicates remote device ready to receive a character (connected to remote RxRTS)

EECC250 - Shaaban #4 lec #12 Winter RS232C Serial Data Interface RS232C is the most commonly used serial data interface in the computer industry. The following diagrams and table give the pinout details for the four most commonly used physical serial data connectors:

EECC250 - Shaaban #5 lec #12 Winter RS232C Serial Connectors Pinout DB9 DB25 RJ45 RJ46 Signal Usual Source CD - Carrier Detect MODEM RxD - Receive Data MODEM TxD - Transmit Data TERMINAL DTR - Data Term’l Ready TERMINAL Signal Ground DSR - Data Set Ready MODEM RTS - Ready to Send TERMINAL CTS - Clear to Send MODEM RI - Ring Indication MODEM 1 1 Earth/Frame Ground Connector Pin #

EECC250 - Shaaban #6 lec #12 Winter Motorola Dual UART (DUART) The Motorola Dual Universal Asynchronous Receiver/Transmitter (DUART) has the following features: Two, independent, full-duplex asynchronous serial Receiver/Transmitter ports: A, B 16, 8-bit registers for data buffering, control and status information. Each Receiver has a 4-byte buffer to hold incoming data. Independently programmable baud rate (bits per second) for each Receiver and Transmitter: 18 Fixed rates: 50 to baud Programmable data format allowing five to eight data bits. Programmable channel modes: Normal (full-duplex). Automatic echo. Versatile interrupt system: Single interrupt output with four maskable interrupting conditions. Interrupt vector output on interrupt acknowledge (IACK).

EECC250 - Shaaban #7 lec #12 Winter DUART Registers Decimal Offset from DUART Base Address Read Write Mode Register Port A (MR1A, MR2A) Status Register Port A (SRA) Do not access Receiver Buffer Port A (RBA) Input Port Change Register (IPCR) Interrupt Status Register (ISR) Current MSB of Counter (CUR) Current LSB of Counter (CUL) Mode Register Port B (MR1B,MR2B) Status Register Port B (SRB) Do not access Receiver Buffer Port B (RBB) Interrupt Vector Register (IVR) Input Port (Unlatched) Start Counter Command Stop Counter Command Mode Register Port A (MR1A, MR2A) Clock Select Register Port A (CSRA) Command Register Port A (CRA) Transmitter Buffer Port A (TBA) Auxiliary Control Register (ACR) Interrupt Mask Register (IMR) Counter/Timer Upper Byte (CTUR) Counter/Timer Lower Byte (CTUL) Mode Register Port B (MR1B,MR2B) Clock Select Register Port B (CSRB) Command Register Port B (CRB) Transmitter Buffer Port B (TBB) Interrupt Vector Register (IVR) Output Port Configuration (OPCR) Output Port Bit Set Output Port Bit Clear

EECC250 - Shaaban #8 lec #12 Winter

EECC250 - Shaaban #9 lec #12 Winter

EECC250 - Shaaban #10 lec #12 Winter DUART+4 DUART+20

EECC250 - Shaaban #11 lec #12 Winter DUART+18DUART+2 DUART+8

EECC250 - Shaaban #12 lec #12 Winter Interrupt Vector Register (IVR) Interrupt vector number: Bit7 - Bit0 DUART+24 DUART+10 (read) DUART+10 (write)

EECC250 - Shaaban #13 lec #12 Winter DUART EQU $0FF800 Base Address of DUART MRA EQU DUART+0Mode Register Port A SRA EQU DUART+2Status Register Port A (read only). CSRA EQU DUART+2Clock Select Register Port A (write only) CRA EQU DUART+4Commands Register Port A (write only) RBA EQU DUART+6Receiver Buffer Port A (read only) TBA EQU DUART+6Transmitter Buffer Port A (write only) ACR EQU DUART+8Auxiliary Control Register ISR EQU DUART+10Interrupt Status Register (read only) IMR EQU DUART+10Interrupt Mask Register (write only) MRB EQU DUART+16Mode Register Port B SRB EQU DUART+18Status Register Port B (read only). CSRB EQU DUART+18Clock Select Register Port B (write only) CRB EQU DUART+20Commands Register Port B (write only) RBB EQU DUART+22Receiver Buffer Port B (read only) TBB EQU DUART+22Transmitter Buffer Port B (write only) IVR EQU DUART+24Interrupt Vector Register DUART Registers Address Equates

EECC250 - Shaaban #14 lec #12 Winter Polled I/O Example Using Port A of DUART Subroutine INITIAL, initializes port A of DUART to send and receive. Subroutine GET_CHAR inputs one character from port A to register D2 when port A receiver is ready with a character using busy-waiting Subroutine PUT_CHAR outputs one character to Port A transmitter from register D0 when port A transmitter is ready. * DUART reset if needed INITIAL MOVE.B#$30,CRAReset Port A transmitter MOVE.B#$20,CRAReset Port A receiver MOVE.B#$10,CRAReset Port A MR (mode register) pointer * Select baud rate, data format, and operating modes in ACR, MR1A, MR2A MOVE.B#$80,ACRSelect baud rate set 2 MOVE.B#$BB,CSRASet both Rx, Tx speeds to 9600 baud MOVE.B#$93,MRASet port A to 8 bit character, no parity * Enable RxRTS output using MR1A MOVE.B#$37,MRASelect normal operating mode *TxRTS, TxCTS, one stop bit using MR2A MOVE.B#$05,CRAEnable Port A transmitter and receiver RTS

EECC250 - Shaaban #15 lec #12 Winter GET_CHAR, PUT_CHAR Subroutines: GET_CHAR, PUT_CHAR * Subroutine GET_CHAR inputs a single character from port A receiver into * register D2 when port A receiver is ready using polling. GET_CHAR NOP IN_POLL MOVE.BSRA,D1Read port A status register SRA BTST#0,D1Test receiver ready bit RxRDY BEQIN_POLLWait until character is received MOVE.BRBA,D2Read character received into D2 RTS * Subroutine PUT_CHAR outputs a single character from register D2 to port A * transmitter when Port A transmitter is ready using polling. PUT_CHAR NOP OUT_POLL MOVE.BSRA,D1Read port A status register SRA BTST#2,D1Test transmitter ready bit TxRDY BEQOUT_POLLWait until transmitter A is ready MOVE.BD0,TBATransmit character to port A RTS

EECC250 - Shaaban #16 lec #12 Winter Interrupt-Driven Terminal Character Input & Echo I/O Example A data terminal is connected to port A of the (receiver & transmitter). An interrupt should be generated every time a character is entered using the terminal keyboard. An interrupt service routine (ISR) for this interrupt should: –Store the character obtained from the terminal (using port A receiver) in a character buffer in memory at the address pointed to by A1 –Echo the character to the terminal’s screen (using transmitter of port A). The two routines needed: initialization subroutine A_INIT, and ISR, A_ISR A_INIT   Point A1 to initial memory character buffer   Initializes Port A of to send and receive with interrupts enabled when a character is received.   Initialize Interrupt Vector Register and exception table entry A_ISR   Store character in memory buffer  Wait until transmitter of port A is ready, then echo character to screen.

EECC250 - Shaaban #17 lec #12 Winter Interrupt-Driven I/O: A_INIT A_VEC EQU 64Vector number for DUART interrupt VEC_ADD EQUA_VEC*4Interrupt vector table address IMRM EQU% * Initialization routine, DUART assumed to have been reset else where ORG$1000 A_INIT LEABUFFER,A1Initialize character buffer pointer LEAA_ISR,A0 MOVE.LA0, VEC_ADDInitialize exception vector table entry * Initialize port A of DUART MOVE.B#$13,MRAInitialize MR1A MOVE.B#$07,MRAInitialize MR2A MOVE.B#$BB,CSRAInitialize CSRA MOVE.B#$05,CRAInitialize CRA MOVE.B#$70,ACRInitialize ACR MOVE.B#A_VEC,IVRLoad interrupt vector in IVR MOVE.B#IMRM, IMRInitialize interrupt mask IMR RTS ORG $1500 BUFFER DS.B256

EECC250 - Shaaban #18 lec #12 Winter Interrupt-Driven I/O: A_ISR * Interrupt service routine A_ISR: * Make sure a character is actually available in receive buffer A, RBA, otherwise return * If a received character is found: read RBA and store in memory character buffer. * then wait until transmitter of port A is ready to transmit then: * echo the character just received to TBA ORG$1200 A_ISR MOVE.BISR,D0 BTST.B#1,D0Verify a character is available in RBA BEQDONEIf none return from interrupt MOVE.BRBA,D1Get character in D1 MOVE.BD1,(A1)+Put character in memory buffer ECHO_W MOVE.BSRA,D2Read port A status register SRA BTST#2,D2Test transmitter ready bit TxRDY BEQECHOIf not ready wait MOVE.BD1,TBAEcho character on screen DONE RTE