Performed by: Ziv Shwaitzer Chen Damishian Instructor: Nitzan Miron המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Subject: סמסטר ( אביב ) תשס " ה 1 Asynchronous Pipelined Ring Interconnection for SoC

Project goals המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Design a system that is composed of different processing elements. Implement the system using the Asynchronous Pipelined Ring Interconnection system. Synthesize the system on an FPGA card. Debug the system and check its feasibility.

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The project is an implementation of a system, which is composed of several processing elements, which operate in parallel, and with different clock frequencies. The processing elements are synchronized using an Asynchronous Piepiled Ring Interconnection platform, which was designed and implemented in the VLSI laboratory. The system that is proposed is a kind of a calculator, which works with a stack architecture.

Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Memec 2vp7ff672-7 board with Virtex II Pro and all supplied peripherals DIP switches. Push Buttons. LCD display. Serial port connection. RS-232 cable Xilinx JTAG parallel port IV cable Host HDL designer 2004 Xilinx EDK 6.3i Terra Pro HyperTerminal

System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Serial port DIP Switches – Used to enter a number between 0 and 255. Push button – Used to enter the numbers or the commands LCD screen – used to display the project information.

FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 DIPPush Asynchronous Ring InputOutput StackMemory ALU