Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #14: Smart Cart 525 Stage XIV: 25 April 2005 Final Presentation

Agenda For Final Presentation Marketing (Bowei) Project Description (Syed) Behavioral/Algorithmic Description (Syed) Design Process (Jenna) Floorplan Evolution (Jenna) Layout (Jonathan) Issues Encountered (Idong) Verification (Idong) Specifications (Jonathan) Conclusions (Bowei)

Marketing Bowei Gai

Shop the way YOU want © 2005 SmartCartGroup

SmartCart525 is a part of a low-cost solution to today’s shopping problems utilizing an encrypted, closed-form, real time all-in-one reader, and transmitter. © 2005 SmartCartGroup

Product Need Problem with Shopping Shopping can be wasteful  Time spent waiting in line  Money spent on hiring extra employees  Retail theft is a $46 billion annual industry! © 2005 SmartCartGroup RFID Solution Like a barcode but…  Omni-directional Line of sight not required  Digital accuracy Availability  Projected to be on every product in a few years  $8 billion by 2008

The Solution Real-Time shopping solution A Close Form solution requiring no additional computation or new shopping carts Onboard data encryption Reduce of the need for a check-out system and personnel We will create an on-cart product monitoring system that will allow for: © 2005 SmartCartGroup

Physical AspectsCost Software encryption Slow, computationally intensive on the processor Much bigger, less durable Higher power consumption Advanced Encryption Standard (Rijndael) Native Dynamic Public and Private Keys for secure data transfer Fast and trusted due to hardware integration Light weight, small size, durable Low power consumption Easy implementation on current carts and shopping baskets The Edge $40 per unit Low production and maintenance cost Each cart equipped with on-board laptop High maintenance cost Security

Marketing and Exit Strategy 2 year technical development process Seek prototype investors for initial funding Market will be ready for a proven product Active testing in live retail environments Outsource and sell to production firm or to be $$bought out$$ by another company.

Project Description Syed Hussain

Our chip will: Take in a 5-bit product ID from RFID receiver to find product price from a lookup table Keep a running total price for items to be purchased (allows for addition/removal of items from cart) Calculate subtotal, tax, total, and take store coupons into account Use Rijndael encryption to securely transmit 32 bit store card information to store’s central computer About the Smart Cart 525

Behavioral/Algorithmic Description

Inserting an item insert Item code Read enable goes high Purchase removing an item remove Done shopping/check out Check out Tax? Encryption Time read store card Coupon price off Add prices in SRAM New price price Write enable goes high

Rijndael Encryption 32bit 9 rounds Add round key: Simple XOR function, XOR’s the Key and the State Byte Sub: Lookup Table/ROM, replaces each byte with a new byte Shift Row: 32bit state in the byte matrix, last row interchanged Wires ab1d f069 ab1d 69f0 Mix column: Multiply column of state matrix, with another matrix Key Expand: Generate different 32bit keys for each Add round Key function using ByteSub and XORS

Top Level Schematic Encryption SRAM Adder Multiplier

Encryption Schematic KEY EXPAND ADD ROUND KEY BYTE SUB SHIFT ROW, Mix Col

Design Process Jenna Fu

Design Process Verilog  schematic  layout  Behavioral  structural Verilog  Transistors/gates  full schematic  Gate/component layout  top level Transistor count fluctuated between 17,456-22,434 throughout project Major design decisions/optimizations  Reduced 128-bit Rijndael encryption Verilog description to 32- bit 2 ROMS instead of 6 ROMS  Number of inputs  Floating point vs. non-floating point  Eliminating demuxes in encryption (enable/reset registers)  Two clocks (fast/slow)

Floorplan

Floorplan Evolution (Pre-layout)

Floorplan Evolution (Mid-layout)

Floorplan Evolution (Final chip layout)

Layout Jonathan Lee

It’s “Just” Layout Encryption Registers Logic SRAM Adder Multiplier

Encryption Layout Initial Permutation Round Permutation Final Text Out SBOX with Control Logic SBOX MixColumn Key Expand

Issues Encountered/Verification Idong Ebong

Issues Encountered SmartCart525 Warfare Populares  Excellent group dynamic… style  Need the story, I’ll sign a book deal for some dough Productivity falling after a few hours on layout  Solution is buffing it up with 10 pushups every hour on the hour  Gradually moved up to 40 then laziness kicked in Minor disliking of the floorplan  Distrusted the idea of sticking to certain sizes and shapes  Artists need room to expand, dream, and perfect Tiiiime is on my side… yes it is  No it ain’t

Roadmap to Chip Verification LVS issues Analog Simulation issues Waveform issues Verification Lessons Successful Full Chip verification

Verification Issues LVS issues  Keep track of changes to schematic!!!  Adhere to metal rules to avoid crazy wiring  Watch out for lower level metal contacts Analog Simulation issues  Run out of hard drive space after 9h 47m into simulation  Never write your simulation files in notepad  S-R flip flops are not enable flip flops  Arguments on the workings of the SRAM  DC Solution error  Unresolved extraction error

Verification Issues Continued Waveform issues  Vdd drops across M1-M2 contacts too big M1 all Vdd  Signal speed distorts results Reduce clock speed

Verification Lessons Aim for speed. Simulations will not take 1d 37m. Bother design manager as much as possible and explore Cadence as much as possible You will never get a meaningful output first time Research unknown blocks earlier Your predicted critical path might not be your real critical path You will dream and wish you had more time for a deep analysis of the design hence try to finish as early as you can

Successful Full Chip Verification Nice Waveform  Matches Schematic and Extracted Simulations  Results correct  Behavioral and Structural verilog concur  Happy campers all around Ultimate Lesson  Simulate every step of the way. Small blocks, top level schematic, extracted, and extractedRC multiple times

Specifications Jonathan Lee

Component Specifications EncryptionMultiplierAdderSRAMRegisters Transistor Count Area (in μm 2 ) Density

Final Specifications Area: x = 92,879.5 μm 2 # of Transistors = 22,120 Density: (transistors/μm 2 ) =.238 Aspect ratio = 1.13 Pin Count = 87 pins - Input  16-bit input, 3-bit operation code - Ouput  32-bit textOut, 21-bit finalPrice, 10-bit lastPrice - vdd!, gnd!, clk, clk2, done Final Clock Speed: 10MHz with the fast clock running at 50MHz

Conclusion Bowei Gai

What's Next? Next Generation System 20 bit FP adder/multiplier 128 bit encryption. No more SRAM, query from central computer Our Vision: Adder/multiplier will get proportionally bigger. Encryption logic will increase proportionally but SBOX will remain the same. Wireless communication unit will be added to the system.

Strategies Understand what’s involved  Do the research, is it a reasonable project? Good floorplan  Good approximations from individual blocks, bit slicing, abutment. Divide and conquer  Detailed specifications. Must meet the specifications. Leave time for testing  Not done after LVS. Think ahead, work ahead. SUCCESS = TEAMWORK x COMMUNICATION

Road Map for the Restless March 26 th – Tepper Business Venture Challenge April 25 th – AMD Sponsored Final Presentation May 4 th – Meeting of the Minds May 7 th – IEEE regional Competition June 27 – EnterPrize Business Plan Competition September TSMC SmartCart525 Prototype June First SmartCart Prototype.