Layout-aware Scan-based Delay Fault Testing Puneet Gupta 1 Andrew B. Kahng 1 Ion Mandoiu 2 Puneet Sharma 1 1 ECE Department, University of California – San Diego 2 CSE Department, University of Connecticut, Storrs

Outline Introduction Introduction Problem formulations Problem formulations Multi-fragment greedy algorithm Multi-fragment greedy algorithm Experiments and results Experiments and results Future directions Future directions

Delay Fault Testing Delay fault: failure of a path to meet timing Delay fault: failure of a path to meet timing Initialization Vector High clock speeds + increasing variability High clock speeds + increasing variability  Delay fault testing important Pair of vectors required Pair of vectors required Initialization vector Initialization vector Launch vector Launch vector Launch Vector 1 0

Scan-based Delay Fault Testing Utilizes standard shift- scan architecture Utilizes standard shift- scan architecture Launch vector produced in two ways: Launch vector produced in two ways: From circuit logic From circuit logic  Functional justification  Functional justification From scan chain From scan chain  Scan justification

Functional Justification Launch vector generated by the circuit logic Launch vector generated by the circuit logic 1.Scan-in initialization vector No effect of scan order No effect of scan order 2. Give system CLK to generate launch vector 3.Give system CLK, capture result 4.Scan-out result Not all paths testable Not all paths testable Difficult to produce vector pairs Difficult to produce vector pairs

Scan Justification Launch vector generated by shifting initialization vector Launch vector generated by shifting initialization vector 1.Scan-in initialization vector 2.Give scan CLK to generate launch vector 3.Give system CLK, capture result 4.Scan-out result Given scan order, not all vector pairs usable Given scan order, not all vector pairs usable Coverage: %age of vector pairs usable Initialization: Launch:

Increasing Scan Coverage Scan order Scan order Initialization: Launch: Don’t cares Don’t cares Initialization: 1 0 x 1 1 Launch: 1 1 x Dummy flops Dummy flops Initialization: Launch:

Scan Order Objectives Coverage driven, layout oblivious Coverage driven, layout oblivious Gupta et al, Cheng et al, … Gupta et al, Cheng et al, … WL: mm, Cov: % WL: 1.22 mm, Cov: 56.80% Layout driven, coverage oblivious Layout driven, coverage oblivious QPlace, Boese et al., Kobayashi et al., … QPlace, Boese et al., Kobayashi et al., … WL: 1.46 mm, Cov: % Layout + Coverage driven Our approach

Outline Introduction Introduction Problem formulations Problem formulations Multi-fragment greedy algorithm Multi-fragment greedy algorithm Experiments and results Experiments and results Future directions Future directions

Scan Chain Ordering Modeled as TSP with flops as cities Modeled as TSP with flops as cities TSP objective TSP objective Minimize WL: MinWL (Boese et al.) Minimize WL: MinWL (Boese et al.) Minimize #dummy for 100% coverage: CompleteDFC (Gupta et al.) Minimize #dummy for 100% coverage: CompleteDFC (Gupta et al.) This paper: Minimize WL + Maximize coverage: MaxDFC This paper: Minimize WL + Maximize coverage: MaxDFC u(i)=0 & v(j)=1 where, u: Initialization vector or u(i)=1 & v(j)=0v: Launch vector Dummy insertion in an edge makes all vector pairs compatible with it Dummy insertion in an edge makes all vector pairs compatible with it Vector pair incompatible with an edge Vector pair incompatible with an edge A vector pair is incompatible with an edge e ij if placing flop j after flop i in the scan chain causes it to become unusable A vector pair is incompatible with an edge e ij if placing flop j after flop i in the scan chain causes it to become unusable Formally, vector pair (u, v) is incompatible with e ij if Formally, vector pair (u, v) is incompatible with e ij if

MinWL (e.g., Boese et al.) Given Given Set of n placed flip-flops F, Scan-in SI, Scan-out SO Find Scan chain ordering  of F  {SI, SO}, starting with SI ending with SO Such that Total scan chain length minimized Total scan chain length minimized

CompleteDFC (Gupta et al.) Given Given Set of n flip-flops F, Scan-in SI, Scan-out SO Set of n flip-flops F, Scan-in SI, Scan-out SO Set of m delay fault vector pairs  Set of m delay fault vector pairs  Find Find Scan chain ordering  of F  {SI, SO}, starting with SI ending with SO Scan chain ordering  of F  {SI, SO}, starting with SI ending with SO Such that Such that # dummy flops required for 100% coverage minimized # dummy flops required for 100% coverage minimized

MaxDFC Given Given Set of n placed flip-flops F, Scan-in SI, Scan-out SO Set of n placed flip-flops F, Scan-in SI, Scan-out SO Set of m delay fault vector pairs,  each with a weight w t, t   Set of m delay fault vector pairs,  each with a weight w t, t   Upped bound on #dummies, D Upped bound on #dummies, D Find Find Scan chain ordering  of F  {SI, SO}, starting with SI ending with SO Scan chain ordering  of F  {SI, SO}, starting with SI ending with SO Set of alive vector pairs, C Set of alive vector pairs, C Such that Such that Scan length minimized Scan length minimized Sum of weights of alive vector pairs maximized Sum of weights of alive vector pairs maximized Vectors pairs incompatible with at most D edges Vectors pairs incompatible with at most D edges

Outline Introduction Introduction Problem formulations Problem formulations Multi-fragment greedy algorithm Multi-fragment greedy algorithm Experiments and results Experiments and results Future directions Future directions

Three Phase MFG - Overview Phase I Phase I Produce D+1 short, high coverage scan chain fragments Produce D+1 short, high coverage scan chain fragments Based on multi-fragment algorithm for TSP Based on multi-fragment algorithm for TSP Data structures Data structures Edge-vector incompatibility matrix Edge-vector incompatibility matrix Edge buckets Edge buckets Phase II Phase II Stitch D+1 fragments using D dummies minimizing WL Stitch D+1 fragments using D dummies minimizing WL Phase III Phase III Further reduce scan chain WL Further reduce scan chain WL

Three Phase MFG – Phase I initialize edge-vector incompatibility matrix distribute edges in buckets based on #incompatible vector pairs while #fragments > #dummies+1 pop shortest edge e ij from first non-empty bucket if( eij is admissible in tour ) add e ij to tour remove vectors incompatible with e ij from edge-vector matrix promote edges with which removed vectors were incompatible 1212121 313131 323232 121212 131313 232323 3131313 23232323 + 5 vectors, 0 dummies edge-vector matrix 012 buckets 12121212 21212121 31313131 32323232

Three Phase MFG – Phase I Scalability Scalability Use small #edges, w(e) < T Use small #edges, w(e) < T If #frags < #dummies + 1, rerun with threshold=M  T If #frags < #dummies + 1, rerun with threshold=M  T Quite insensitive to T, M Quite insensitive to T, M

Three Phase MFG – Phase II Target: Stitch D+1 fragments, minimizing WL Target: Stitch D+1 fragments, minimizing WL Approach Approach ATSP with fragments as cities ATSP with fragments as cities D1 D2 w e  WL required to connect fragments w e  WL required to connect fragments Small #cities Small #cities  Quick even with high quality TSP solver

Three Phase MFG – Phase III Target: Further reduce scan WL Target: Further reduce scan WL Approach Approach Create TSP instance with flops as cities Create TSP instance with flops as cities Throw in edges compatible with all alive faults Throw in edges compatible with all alive faults w e  WL of edge e w e  WL of edge e D1 D D1 D D1 D2

Outline Introduction Introduction Problem formulations Problem formulations Multi-fragment greedy algorithm Multi-fragment greedy algorithm Experiments and results Experiments and results Future directions Future directions

Experimental Flows Comparison of three flows Comparison of three flows MinWL (Boese et al.) MinWL (Boese et al.)  Reference min WL tour CompleteDFC (Gupta et al.) CompleteDFC (Gupta et al.)  Reference full coverage tour MaxDFC MaxDFC

Testcases Testcase # cells # flops # paths Functional coverage s % s % s % AES % DES % Synthesis Design Compiler STAPrimeTimeATPGTetraMAX PlacementQPlace Source all vectors scanvectorsfloplocations paths func vectors 

Results: s38417 Wirelength Wirelength Coverage Coverage MinWLMaxDFC

Results: aes Wirelength Wirelength Coverage Coverage MinWLMaxDFC

MFG Scalability MFG Runtime Time(s)

Dummy-Coverage Tradeoff Proposed ILP formulation Proposed ILP formulation s38417

Outline Introduction Introduction Problem formulations Problem formulations Multi-fragment greedy algorithm Multi-fragment greedy algorithm Experiments and results Experiments and results Future directions Future directions

Conclusions We proposed an algorithm to simultaneously reduce WL and increase delay fault coverage We proposed an algorithm to simultaneously reduce WL and increase delay fault coverage Significant increase in coverage with 10-30% WL increase Significant increase in coverage with 10-30% WL increase Explored tradeoff b/w coverage and dummy insertion Explored tradeoff b/w coverage and dummy insertion

Future Directions Extension to multiple scan chains Extension to multiple scan chains Congestion aware scan ordering Congestion aware scan ordering Modifications to use compacted and/or redundant vectors Modifications to use compacted and/or redundant vectors

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