CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 1 Tridas Status Drew Baden University of Maryland March 2004

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 2 Timing signals - Overview Rack-to-Rack CAT 7 HTRHTR DCCDCC HTRHTR HTRHTR HTRHTR FANOUTFANOUT HTRHTR DCCDCC HTRHTR HTRHTR HTRHTR FANOUTFANOUT FANOUTFANOUT FANOUTFANOUT FANOUTFANOUT TTC Minicrate TTC Stream (“RX_CLK”) HCAL VME Crates ECAL

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 3 Fanout board 2 operating modes: Global or Crate TTC fiber Clk80 Input from GLOBAL Fanout 18 Outputs 40MHz RX_CLK = 40MHz RX_BC0 INT_BC0 RX_CLK = 40MHz RX_BC0 QPLL EXT 80MHz QPLL can run stand-alone TTCrx EXT_BC0 FPGA Delay TTC Broadcast G G G C C C G

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 4 Complete path of a 40MHz RX_CLK TTC fiber CLK40_Des1 FPGA CAT7 (RX_CLK, RX_BC0) TTCrx QPLL FPGA TTCrx QPLL Fanout board in Crate-mode Fanout board in Global-mode 3.3V CMOS Path is 3.3V differential PECL unless otherwise stated. Path of RX_BC0 is similar but comes from the FPGA rather the QPLL In the Global-mode card, do not mount the buffers for CLK80 and TTC CAT7 (RX_CLK, RX_BC0, TTC, CLK80) HTR SLB Max skew on HTR traces is 0.7 ns. Spec is: Skew <  6 ns across HCAL and ECAL

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 5 Fanout/TTC_UMD Cards New design complete, cards made, prototypes produced –1 sent to FNAL, UMD, CERN + Princeton –Waiting for confirmation, then will go into production TTC_UMD Mezzanine card –Carry TTCrx onto HCAL boards (HTR, DCC, Fanout) –All boards produced, parts are all in –Off to the assembler Mar 15 –Expect to have them all back and ready for checkout in ~2 weeks –Building mass tester now

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 6 DCC Status DCCv4 (used in TB03) – 8 exist DCCv5 – identical to v4 except for new front panel w/LEDs –LED “boards” are produced –Now ordering 10 new logic boards –Plan to have “a few” ready by May (E. Hazen) –Can provide new firmware for all existing v4s Main firmware change is in the input channel numbering –Planning to change the 10-pin RJ45 connectors on the LRBs to match the new variety New connectors prevent inadvertent insertion of 8-pin RJ45 connectors and bending the pins

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 7 Changes to HTR for Rev4 Clocking issues –No earth-shaking changes –No evidence of any difficulties associated with HTR layout/implementation “Cosmetic” changes –Moved 2 LC’s down to giver more clearance for fibers –Removed hot swapping circuits Worry about noise, decided not to require HTR to be hot swappable –Front-panel changes –Bias resistors for all differential pair inputs (a powerup issue only…) –Change DCC 10-pin connectors Fanout input is 8-pin standard RJ45 Eliminate possibility of plugging Fanout cable into DCC connector, munging pins –Changes to VME to accommodate software (Big/Little Endian defaults) Miscellaneous changes –Fixed what was found to be wrong with Rev3 board, add test points, other minor stuff

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 8 Changes to HTR for Rev4 (cont) Changes necessary for SLB –Optimized critical clock and data lines –HTR 40MHz “LHC” clock to come from TTC TPG data and TTC broadcast need to have synchronization –Added hardware reset circuitry for TTCrx –Deal with SLB startup current –Added separate SLB JTAG chain

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 9 HTR Schematic SLB RX_CLK40 SLB RX_BC0 TTC TTCrx CLK80 Crystal Serial Optical Data Ref Clk Deserializers (8) 20 Recovered Clk TPG Path SYS40 Clk TTC Broadcast Async Fifo PLL TTC 40 Clk x2 XILINX LC Fiber Data Princeton Fanout Card (1/VME crate) SYS80 Clk

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 10 HTR Rev4 Status Current (Rev4) board – 3 in lab now –Testing:  Links/Clocks (same as Rev3, no problems, no mystery at UMD)  DCC path (not yet, but same as Rev3)  TPG path (so far so good) –Localbus access of SLB verified –SLB/Wisconsin receiver board 1.2Gbaud copper link: verified »Again, success here depended on having a precision 120MHz clock –Jose Carlos da Silva is debugging SLB now...95% working. »Wisconsin tests boards were not built for debugging anything except the link –Will concentrate on whether we can use cat6 quad twisted pair instead of “Wesley” cables (2 dual coax) –Just a few layout changes needed, ready for production

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 11 HTR Production Status Production –Working on contracting with vendors for Fab and Assembly Will be ~$90k for each. Causes Maryland purchasing dept tempature to rise... Would like to be ready for production this summer –Should we wait for Vertical Slice in sept? Not necessary. Integration tests in Madison (May/June) will be good enough. Would like to begin when ready. Maybe June, TBD depending on more Level 1 integration tests, and Testbeam results

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 12 HTR Near Term Plans Production verification: waiting for more Level 1 (HTR/SLB/Wisconsin) tests before “pushing the button” –Checks on synch, latency, etc. Testbeam04: Plan to run some Rev4s –Want to check out under battle conditions –Issues: Only have 3 now. Rev3 and Rev4 are not compatible over VME –Would require changes to Jeremy’s DAQ –Will send 2 of the new Rev4s to CERN. These can be used for (e.g.) HF which needs 2 or fewer HTRs to run

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 13 Test Boards Front-end emulators –1 at CERN, 1 at UMD. More being stuffed now. Trigger Link Receiver boards –For sending data to RCT Vitesse receiver boards In a systm which is in our control For production AND for commissioning Programmable logic –Will build this capability into the HTR Use existing SLB sites, run backwards into XILINX Sandwich interface board in between Wisconsin receiver and existing HTR daughterboard site –Complete documentation from Wisconsin in January, board is now under design Estimate another ~month in the lab for testing. HTR SLB site UW Vitesse receiver mezzanine card

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 14 Level 1 Latency ItemHBHEHF BX to QIE input224 QIE to GOL (FE)998 Optical Link ( HTR → SLB12 SLB ?444 TPG Cables (15m)333 TOTAL HCAL O-E QIECCA HTR SLB RCT BX TOF To RBX DataTo RCT RBX HPD or PMT (HF) 46 clocks = 1,147.7ns GOL Nothing has changed (46 clock tick budget) –FPGA logic does not include summing! –Estimates: probably 1 more clock cycle in HF Would change HTR → SLB from 12 to 13 Would try some hand routing inside Xilinx to recover it...have not done it yet –Eliminating summing in overlap might be ok for MET/Jet triggers But would still have the 1→ 6 summing in HF –Overall still have a problem with optical cables, need to consider summing next 12-13

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 15 TPG Alignment Align so that all ECAL and HCAL data from same bucket reaches RCT inputs at same time –Achieved by delaying each channel individually –Method for establishing this delay implemented inside SLB Histogram data over threshold, look for LHC structure pattern –Issue: For some detectors, occupancy is very low (HO, especially at low lumens) Some results from Salavat... Ch N Ch N+1 Ch N+2 Global BC0

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 16 Absolute (and Relative) Timing Relative timing within HCAL via: –Laser and LEDs Have to consider random latency variation after resynching optical links –BC0 message from FE Absolute synchronization for Level 1 –SLB histograms ET –Looks for LHC beam structure –Does this work? (esp at low luminosity?) Salavat has been working on this –Min bias events, some with Orca and some with fast sim Occupancy at shown here –250MeV per ADC count Question: how many orbits to establish the LHC beam structure per detector?

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 17 Summary (from Salavat) HCAL ElementCut (ADC counts) # LHC Orbits Required (88  s/orbit) HB,  ~0 ≥65x10 5 HB,  ~1.4 ≥610 5 HE,  ~1.6 ≥510 4 HE,  ~2.8 ≥510 2 HF, 13,  ~2.9 ≥510 4 HF, 13,  ~3.4 ≥510 3 HO, ring 2≥8>10 7

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 18 Summary (from Salavat) For HB, HE, and HF probably easy to remeasure “on the fly” –Fill SLB histograms, read out over VME, calculate offset… For HO, probably will take few hours to maybe even a day –OK as long as absolute (non random) latency is stable over long periods –Need more simulation, checks…in progress

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 19 Occupancy Implications and Alignment Bottom line: Will try to develop the following algorithm: –Whatever it takes, we measure the absolute alignment If it takes hours, then so be it... –We hope that this absolute alignment will not change over time –Keep track of the relative alignment by: Sending up a BC0 signal from the FE –Keep track of this. If the links go down and we reset, then we measure the relative alignment and adjust accordingly Problems: –If we are off by an order of magnitude or more...  Needs some more simulation, computing resources, etc. –Assumes long term stabilities which will have to be tracked

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 20 Another Latency Issue TTCrx chip has a chip-to-chip variation in latency of ~20ns –Each chip will be stable from powerup-to-powerup But...there will be a voltage and temperature dependence How well known is this? Need a scheme for insitu calibration of the TTCrx latency –Probably can come up with something for HTR/DCC/Fanout –Not sure what to do about TTCrx in FE...

CMS/HCAL/TriDas. Mar, 2004 HCAL TriDAS 21 Longterm Schedule