1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.

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Presentation transcript:

1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Supervisor: Evgeny Fiksman Performed by: Moshe Bino Alex Tikh Spring 2007

2 Table of Contents General p.3 Project goals p.4 Software p.5 Hardware p.6-8 Block diagram p.9 Test & debug p Time table p.12-14

3 General Programmable hardware chips present a wide base for developing SOPC systems. SOPC systems include generic soft-core processor called Microblaze and basic programmable elements. MPI – Message Passing Interface enable working with fast communication.

4 Implementation of mini distributed core system using MPI router. Build an infrastructure for fast communication in multi-core system. Build a designated C/C++ application to show the advantages of working with parallel system. Project goals

5 Software Embedded Development Kit (EDK) is a suite of tools and IP* that enables to design a complete embedded processor system. Integrated Software Environment (ISE) - software development tools that allow to circumvent some of designing complexity. Development environment * IP = Intellectual property

6 Hardware The Virtex-II Pro FPGA contain platform for designs that are based on IP cores and customized modules. The MicroBlaze core is a 32-bit RISC* Harvard architecture soft processor core with 32 general purpose registers, ALU, and a rich instruction set optimized for embedded applications. Development environment *RISC = Register Instruction Set Computer

7 Hardware The top design will include 4 MicroBlaze processors connected by direct point to point Fast Simplex Links (FSLs) for interprocessor communication. FSL Bus is a uni-directional point-to-point communication channel bus used to perform fast communication between any two design elements on the FPGA when implementing an interface to the FSL bus. Configuration

8 Hardware Kit used – XUP Virtex - II Pro Board

9 Block diagram

10 Test & Debbug ModelSim is a simulation and debug environment, combining high performance with powerful and intuitive GUI. Unit test ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile software cores directly into your design, allowing to view any internal signal or node, including embedded hard or soft processors.

11 Test & Debug Chip scope pro system block diagram

12 Run a test application - create small application and look for expected results. If expectations are not met, debug with Xilinx Microprocessor Debugger tool (XMD) which is a software debugger for a multi- processor system. System test Test & Debbug

13 Time Table – Mid Term Studying EDK environment.1 Week ~ Studying FSL interface.1 Week ~ Define Simple MPI / MPP1 Week ~ Build a dual core system (without FSL connectivity) 1 Week ~ High level design1 Week ~ Midterm presentationtentative

14 Time Table – first semester Continue design to low level3 Week Implementing FSL connectivity 2 Week Preparing report2 Week End semester presentation1 Week

15 Time Table – second semester Build a quad core system Implementing router for 4 processors Test and debug Run a test application

16 QUESTIONS ?