CS 161, Spring 2006 Test 2 Answers

Q1(a) +10 = in 2’s complement. And in sign-extended -12 = in 2’s comp And in sign-extend

MULTIPLY HARDWARE Lect 8, Slide 10 Combine Multiplier register and Product register 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Product (Multiplier) Multiplican d 32-bit ALU Write Control 32 bits 64 bits Shift Right

Q1 c Action Product + MultiplierMultiplicand Start Shift Add Shift Shift Shift Result =

Q2. Slide 4, Lecture 10 Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALUcon RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion Imem “4” PCPC addadd addadd << 2 MuxMux PCSrc “Left Shift 2” module What about jump?

Q 2 (a) Slide 10 Lect 11

Q2 (c) Total cycle time = 2 (Inst read) +1 (reg read) + 2 (ALU) + 2 (Data read) + 1 (reg write) = 8 ns => 125 MHZ R-type = = 6 ns BEQ = (ALU comp) + 1 (address add) = 6 ns

Q2 (c) Slide 16 Lect 11 Registers Read Reg1 ALUALU Read Reg2 Write Reg Data PCPC Address Instruction or Data Memory MIPS-lite Multicycle Version A B ALU- Out Instruction Register Data Memory Data Register Read data 1 Read data 2 One ALU (no extra adders) One Memory (no separate Imem, Dmem) New Temporary Registers (“clocked”/require clock input)

Q3 (a) Maximum time for any stage in multicycle datapath = 2 ns Hence, cycle time = 2ns => 500 MHz computer R-type = 4 cycles BEQ = 3 cycles Q3 (c) (2 pts) Hardwired Control – Draw the state diagram, FSM, and implement using logic gates or PLA. Microprogram: Design microinstruction format, precompute the control signals, store in ROM, and read them out every cycle (2 pts) Adv/Disdv: Hardwired control is fast but inflexible because instructions cannot be changed. Microprogam is slow due to ROM read in every cycle, but flexible because ROM can be reprogrammed or changed.

Q3 (b) Slide 4 Lect 12