Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Lecture 3 - Instruction Sets Fall 2004 Reading: Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s Slides - Fall 1999 CMU other sources as noted

ECE Fall 2004Lecture 3 - Instruction Sets2 Roadmap for the Term: Major Topics  Computer Systems Overview  Technology Trends  Instruction Sets (and Software)   Logic and Arithmetic  Performance  Processor Implementation  Memory Systems  Input/Output

ECE Fall 2004Lecture 3 - Instruction Sets3 Outline - Instruction Sets  Instruction Set Overview  Classifying Instruction Set Architectures (ISAs)   Some Example Architectures  CISC vs. RISC Architectures  MIPS Instruction Set  Software Concerns

ECE Fall 2004Lecture 3 - Instruction Sets4 What is Instruction Set Architecture?  Specification of the hardware/software interface Software - binary instructions generated by compiler Hardware - interprets and executes instructions  Specification of features visible to programmer  Specification of function for hardware designer

ECE Fall 2004Lecture 3 - Instruction Sets5 What does an ISA Specify?  Supported data types (e.g. byte, short, word, long, float, double )  Memory organization  Registers  Instructions  Function  Operands - number and type Memory operands Register operands  Format and encoding

ECE Fall 2004Lecture 3 - Instruction Sets6 Classifying ISAs based on Operands  Accumulator (e.g. 68HC11)  1 address add A acc  acc + mem[A]  1+x address addx A acc  acc + mem[A + x]  General Purpose Register / Register-Memory (e.g. 80x86)  2 address add Ra B Ra  Ra + mem[B]  3 address add Ra Rb C Ra  Rb + mem[C]  General Purpose Register / Register-Register (e.g. MIPS)  3 address add Ra Rb RcRa  Rb + Rc load Ra A Ra  mem[A] store Ra A mem[A]  Ra  Stack  0 address add tos  tos + next push A pop A (tos = top of stack)

ECE Fall 2004Lecture 3 - Instruction Sets7 Comparing ISA Classes Register-MemoryRegister-RegisterStackAccumulator StoreC AddB LoadA StoreR3, C AddR3,R1,B LoadR1,A StoreR3,C AddR3,R1,R2 LoadR2,B LoadR1,A Add PushB PushA PopC  Code sequence for C = A+B in each class:

ECE Fall 2004Lecture 3 - Instruction Sets8 More About General Purpose Registers  Why do almost all new architectures use GPRs?  Registers are much faster than memory (even cache) Register values are available immediately When memory isn’t ready, processor must wait (“stall”)  Registers are convenient for variable storage Compiler assigns some variables just to registers More compact code since small fields specify registers (compared to memory addresses) RegistersCache Memory Processor Disk

ECE Fall 2004Lecture 3 - Instruction Sets9 Outline - Instruction Sets  Instruction Set Overview  Classifying Instruction Set Architectures (ISAs)  Some Example Architectures   CISC vs. RISC Architectures  MIPS Instruction Set  Software Concerns

ECE Fall 2004Lecture 3 - Instruction Sets10 Review: MC68HC11 Architecture ADDA 42 ABA BEQ 0x0000 0x0001 0x0002 0x0003 0xfffe 0xffff 8 bits Memory (Max 65KB) AB X Y SP PC=0x0002 CCR 16 bits 8 bits Registers 16 bits opcode pre-opcodeopcode operand opcodeoperand opcode Instruction Formats (Variable-length 1-4 bytes)

ECE Fall 2004Lecture 3 - Instruction Sets11 Example Architecture: 80x86 (IA-32) Instruction Formats not shown (Variable Length: see next page) EIP (PC) =0x C (condition codes) EAX ECX EDX EBX ESP EBP ESI EDI CS SS DS ES FS GS EIP EFLAGS bits Registers Memory (Max. 4GB) 0x x x x C 0x x x x C 0xfffffffc 32 bits

ECE Fall 2004Lecture 3 - Instruction Sets12 Some 80x86 Instruction Formats JE offsetcond 44 8 OffsetCALL 832 MOVpostbytedispl. dw regPUSH regADD w 1 Offset 32 ADD w Offsetpostbyte w bit - species operand of byte or 32-bit “double word” d bit - indicates direction of move (register/mem or mem/register) Variable Instruction Length - 1 to 17 bytes

ECE Fall 2004Lecture 3 - Instruction Sets13 Example Architecture: MIPS Memory (Max. 4GB) 0x x x x C 0x x x x C 0xfffffffc 32 bits 32 General Purpose Registers R0 R1 R2 R30 R31 PC = 0x C 32 bits Registers 32 oprsrtoffset oprsrtrdfunctshamt opaddress Instruction Formats (Fixed Length)

ECE Fall 2004Lecture 3 - Instruction Sets14 Outline - Instruction Sets  Instruction Set Overview  Classifying Instruction Set Architectures (ISAs)  Some Example Architectures  CISC vs. RISC Architectures   MIPS Instruction Set  Software Concerns

ECE Fall 2004Lecture 3 - Instruction Sets15 Classifying Architectures: CISC vs. RISC  CISC - Complex Instruction Set  Usually evolved over time (e.g >8086->IA-32)  Many instructions targeted to high-level functions  Large number of instruction formats and instructions  RISC - Reduced-Instruction Set Computers  Small number of fixed length instruction formats  Limited access to memory (load/store architecture) Instructions chosen to make implementation easier, faster  Rely on compiler for higher-level functions  Over time, the distinction has blurred

ECE Fall 2004Lecture 3 - Instruction Sets16 Some Well-Known Architectures +Application - E=Embedded, D=Desktop, S=Server

ECE Fall 2004Lecture 3 - Instruction Sets17 Microprocessor Usage Figure 1.2

ECE Fall 2004Lecture 3 - Instruction Sets18 Outline - Instruction Sets  Instruction Set Overview  Classifying Instruction Set Architectures (ISAs)  Some Example Architectures  CISC vs. RISC Architectures  MIPS Instruction Set   Overview  Registers and Memory  Instructions  Software Concerns